arch: arm64: Reword comments
Fix, reword and rework comments. Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This commit is contained in:
Carlo Caione
Ioannis Glaropoulos
parent
9e897ea2c3
commit
78b5e5563d
6 changed files with 50 additions and 95 deletions
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@ -4,9 +4,8 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief ARM64 Cortex-A power management
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/*
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* ARM64 Cortex-A power management
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*/
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#include <toolchain.h>
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@ -4,9 +4,8 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief ARM64 Cortex-A ISRs wrapper
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/*
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* ARM64 Cortex-A ISRs wrapper
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*/
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#include <toolchain.h>
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@ -20,15 +19,13 @@ _ASM_FILE_PROLOGUE
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GDATA(_sw_isr_table)
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/**
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* @brief Wrapper around ISRs when inserted in software ISR table
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/*
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* Wrapper around ISRs when inserted in software ISR table
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*
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* When inserted in the vector table, _isr_wrapper() demuxes the ISR table
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* using the running interrupt number as the index, and invokes the registered
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* ISR with its corresponding argument. When returning from the ISR, it
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* determines if a context switch needs to happen.
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*
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* @return N/A
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*/
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GTEXT(_isr_wrapper)
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@ -9,24 +9,22 @@
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#ifdef _ASMLANGUAGE
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/**
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* @brief Save volatile registers
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/*
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* Save volatile registers, x30, SPSR_EL1 and ELR_EL1
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*
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* Save the volatile registers and x30 on the process stack. This is
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* needed if the thread is switched out because they can be clobbered by the
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* ISR and/or context switch.
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*
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* @return N/A
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*/
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.macro z_arm64_enter_exc xreg0, xreg1
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/*
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* Two things can happen:
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* Two things can happen to the remaining registers:
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*
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* - No context-switch: in this case x19-x28 are callee-saved register
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* so we can be sure they are not going to be clobbered by ISR.
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* - Context-switch: the callee-saved registers are saved by
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* z_arm64_pendsv() in the kernel structure.
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* z_arm64_context_switch() in the kernel structure.
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*/
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stp x0, x1, [sp, #-16]!
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stp x2, x3, [sp, #-16]!
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@ -39,45 +37,22 @@
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stp x16, x17, [sp, #-16]!
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stp x18, x30, [sp, #-16]!
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/*
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* Store SPSR_ELn and ELR_ELn. This is needed to support nested
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* exception handlers
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*/
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mrs \xreg0, spsr_el1
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mrs \xreg1, elr_el1
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stp \xreg0, \xreg1, [sp, #-16]!
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.endm
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/**
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* @brief Restore volatile registers and x30
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/*
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* Restore volatile registers, x30, SPSR_EL1 and ELR_EL1
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*
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* This is the common exit point for z_arm64_pendsv() and _isr_wrapper(). We
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* restore the registers saved on the process stack including X30. The return
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* address used by eret (in ELR_ELn) is either restored by z_arm64_pendsv() if
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* a context-switch happened or not touched at all by the ISR if there was no
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* context-switch.
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*
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* @return N/A
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* This is the common exit point for z_arm64_svc() and _isr_wrapper().
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*/
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.macro z_arm64_exit_exc xreg0, xreg1
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/*
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* Restore SPSR_ELn and ELR_ELn. This is needed to support nested
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* exception handlers
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*/
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ldp \xreg0, \xreg1, [sp], #16
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msr spsr_el1, \xreg0
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msr elr_el1, \xreg1
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/*
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* In x30 we can have:
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*
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* - The address of irq_unlock() in swap.c when swapping in a thread
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* that was cooperatively swapped out (used by ret in
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* z_arm64_call_svc())
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* - A previos generic value if the thread that we are swapping in was
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* swapped out preemptively by the ISR.
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*/
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ldp x18, x30, [sp], #16
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ldp x16, x17, [sp], #16
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ldp x14, x15, [sp], #16
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@ -90,10 +65,9 @@
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ldp x0, x1, [sp], #16
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/*
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* In general in the ELR_ELn register we can find:
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* In general in the ELR_EL1 register we can find:
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*
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* - The address of ret in z_arm64_call_svc() in case of arch_swap()
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* (see swap.c)
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* - The address of ret in z_arm64_call_svc()
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* - The address of the next instruction at the time of the IRQ when the
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* thread was switched out.
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* - The address of z_thread_entry() for new threads (see thread.c).
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@ -101,10 +75,8 @@
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eret
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.endm
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/**
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* @brief Increment nested counter
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*
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* @return N/A
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/*
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* Increment nested counter
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*/
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.macro inc_nest_counter xreg0, xreg1
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@ -114,10 +86,8 @@
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str \xreg1, [\xreg0, #_kernel_offset_to_nested]
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.endm
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/**
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* @brief Decrement nested counter
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*
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* @return N/A
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/*
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* Decrement nested counter
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*/
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.macro dec_nest_counter xreg0, xreg1
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@ -4,9 +4,8 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Reset handler
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/*
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* Reset handler
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*
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* Reset handler that prepares the system for running C code.
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*/
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@ -22,15 +21,15 @@ _ASM_FILE_PROLOGUE
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/*
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* Platform may do platform specific init at EL3.
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* The function implementation must preserve callee saved registers as per
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* Aarch64 ABI PCS.
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* AArch64 ABI PCS.
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*/
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WTEXT(z_arch_el3_plat_init)
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SECTION_FUNC(TEXT,z_arch_el3_plat_init)
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ret
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/**
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*
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* @brief Reset vector
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/*
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* Reset vector
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*
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* Ran when the system comes out of reset. The processor is in thread mode with
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* privileged level. At this point, neither SP_EL0 nor SP_ELx point to a valid
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@ -38,18 +37,11 @@ ret
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*
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* When these steps are completed, jump to z_arm64_prep_c(), which will finish
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* setting up the system for running C code.
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*
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* @return N/A
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*/
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GTEXT(__reset)
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SECTION_SUBSEC_FUNC(TEXT,_reset_section,__reset)
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/*
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* The entry point is located at the __reset symbol, which is fetched by a XIP
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* image playing the role of a bootloader, which jumps to it, not through the
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* reset vector mechanism. Such bootloaders might want to search for a __start
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* symbol instead, so create that alias here.
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*/
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GTEXT(__start)
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SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)
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@ -58,6 +50,11 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)
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switch_el x1, 3f, 2f, 1f
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3:
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/*
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* Zephyr entry happened in EL3. Do EL3 specific init before
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* dropping to lower EL.
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*/
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/* Initialize VBAR */
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msr vbar_el3, x19
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isb
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@ -67,7 +64,7 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)
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add x0, x0, #(CONFIG_ISR_STACK_SIZE)
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mov sp, x0
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/* Initialize sctlr_el3 to reset value */
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/* Initialize SCTLR_EL3 to reset value */
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mov_imm x1, SCTLR_EL3_RES1
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mrs x0, sctlr_el3
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orr x0, x0, x1
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@ -75,9 +72,9 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)
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isb
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/*
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* Disable access traps to EL3 for CPACR, Trace, FP, ASIMD,
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* SVE from lower EL.
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*/
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* Disable access traps to EL3 for CPACR, Trace, FP, ASIMD,
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* SVE from lower EL.
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*/
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mov_imm x0, CPTR_EL3_RES_VAL
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mov_imm x1, (CPTR_EL3_TTA | CPTR_EL3_TFP | CPTR_EL3_TCPAC)
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bic x0, x0, x1
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@ -88,10 +85,6 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)
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/* Platform specific configurations needed in EL3 */
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bl z_arch_el3_plat_init
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/*
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* Zephyr entry happened in EL3. Do EL3 specific init before
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* dropping to lower EL.
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*/
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/* Enable access control configuration from lower EL */
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mrs x0, actlr_el3
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orr x0, x0, #(ACTLR_EL3_L2ACTLR | ACTLR_EL3_L2ECTLR \
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@ -99,7 +92,7 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)
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orr x0, x0, #(ACTLR_EL3_CPUACTLR | ACTLR_EL3_CPUECTLR)
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msr actlr_el3, x0
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/* Initialize sctlr_el1 to reset value */
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/* Initialize SCTLR_EL1 to reset value */
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mov_imm x0, SCTLR_EL1_RES1
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msr sctlr_el1, x0
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@ -137,9 +130,7 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)
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mov x0, #(CPACR_EL1_FPEN_NOTRAP)
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msr cpacr_el1, x0
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/*
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* Enable the instruction cache and el1 stack alignment check.
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*/
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/* Enable the instruction cache and EL1 stack alignment check. */
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mov x1, #(SCTLR_I_BIT | SCTLR_SA_BIT)
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mrs x0, sctlr_el1
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orr x0, x0, x1
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@ -4,12 +4,11 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Thread context switching for ARM64 Cortex-A
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/*
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* Thread context switching for ARM64 Cortex-A (AArch64)
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*
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* This module implements the routines necessary for thread context switching
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* on ARM64 Cortex-A.
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* on ARM64 Cortex-A (AArch64)
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*/
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#include <toolchain.h>
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@ -23,8 +22,8 @@ _ASM_FILE_PROLOGUE
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GDATA(_kernel)
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/**
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* @brief Routine to handle context switches
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/*
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* Routine to handle context switches
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*
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* This function is directly called either by _isr_wrapper() in case of
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* preemption, or z_arm64_svc() in case of cooperative switching.
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@ -36,7 +35,7 @@ SECTION_FUNC(TEXT, z_arm64_context_switch)
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ldr x2, =_thread_offset_to_callee_saved
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add x2, x2, x1
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/* Store rest of process context including x30 */
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/* Store callee-saved registers */
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stp x19, x20, [x2], #16
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stp x21, x22, [x2], #16
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stp x23, x24, [x2], #16
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@ -85,14 +84,12 @@ SECTION_FUNC(TEXT, z_arm64_context_switch)
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/* Return to z_arm64_svc() or _isr_wrapper() */
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ret
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/**
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* @brief Service call handler
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/*
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* Synchronous exceptions handler
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*
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* The service call (SVC) is used in the following occasions:
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* - Cooperative context switching
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* - IRQ offloading
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*
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* @return N/A
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*/
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GTEXT(z_arm64_svc)
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@ -129,8 +126,9 @@ offload:
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context_switch:
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/*
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* Retrieve x0 and x1 from the stack:
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*
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* - x0 = new_thread->switch_handle = switch_to thread
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* - x1 = x1 = &old_thread->switch_handle = current thread
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* - x1 = &old_thread->switch_handle = current thread
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*/
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ldp x0, x1, [sp, #(16 * 10)]
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@ -4,9 +4,8 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Populated vector table
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/*
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* Populated vector table
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*/
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#include <toolchain.h>
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@ -58,6 +57,7 @@ _ASM_FILE_PROLOGUE
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/* The whole table must be 2K aligned */
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.align 11
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SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,_vector_table)
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/* Current EL with SP0 / Synchronous */
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