From 788714de207d4e4ccdd9a01bb9a449d15d9f08e1 Mon Sep 17 00:00:00 2001 From: Jun Lin Date: Wed, 27 Apr 2022 16:49:26 +0800 Subject: [PATCH] driver: clock_control: npcx: don't gate the eSPI clock if eSPI is defined In the EC application, the system may jump between two built Zephyr images when necessary. If we gate the eSPI clock at initialzation, it will make the eSPI configuration which established by previous image break and lost the communication between EC and host. Signed-off-by: Jun Lin --- drivers/clock_control/clock_control_npcx.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/clock_control/clock_control_npcx.c b/drivers/clock_control/clock_control_npcx.c index 91298edb7aa..6998fd9145e 100644 --- a/drivers/clock_control/clock_control_npcx.c +++ b/drivers/clock_control/clock_control_npcx.c @@ -218,7 +218,12 @@ static int npcx_clock_control_init(const struct device *dev) NPCX_PWDWN_CTL(pmc_base, NPCX_PWDWN_CTL3) = 0x1F; /* No GDMA_PD */ NPCX_PWDWN_CTL(pmc_base, NPCX_PWDWN_CTL4) = 0xFF; NPCX_PWDWN_CTL(pmc_base, NPCX_PWDWN_CTL5) = 0xFA; +#if CONFIG_ESPI + /* Don't gate the clock of the eSPI module if eSPI interface is required */ + NPCX_PWDWN_CTL(pmc_base, NPCX_PWDWN_CTL6) = 0xEF; +#else NPCX_PWDWN_CTL(pmc_base, NPCX_PWDWN_CTL6) = 0xFF; +#endif #if defined(CONFIG_SOC_SERIES_NPCX7) NPCX_PWDWN_CTL(pmc_base, NPCX_PWDWN_CTL7) = 0xE7; #elif defined(CONFIG_SOC_SERIES_NPCX9)