boards: arm: nucleo_f746zg: Activate CAN on nucleo F746zg
This commit adds CAN support for nucleo F746zg. Furtermore CAN was added in stm32f7.dtsi and pinmuc_stm32f7.h CAN_RX: PD0, CAN_TX: PD1 Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
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917cb432ee
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78714b4ff4
6 changed files with 44 additions and 0 deletions
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@ -100,3 +100,11 @@ arduino_spi: &spi1 {};
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&rtc {
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status = "ok";
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};
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&can1 {
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bus-speed = <125000>;
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sjw = <1>;
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prop_seg_phase_seg1 = <6>;
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phase_seg2 = <5>;
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status = "ok";
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};
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@ -20,3 +20,4 @@ supported:
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- watchdog
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- rtc
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- counter
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- can
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@ -62,6 +62,10 @@ static const struct pin_config pinconf[] = {
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{ STM32_PIN_PA6, STM32F7_PINMUX_FUNC_PA6_SPI1_MISO },
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{ STM32_PIN_PA7, STM32F7_PINMUX_FUNC_PA7_SPI1_MOSI },
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#endif /* CONFIG_SPI_1 */
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#ifdef CONFIG_CAN_1
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{STM32_PIN_PD0, STM32F7_PINMUX_FUNC_PD0_CAN_RX},
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{STM32_PIN_PD1, STM32F7_PINMUX_FUNC_PD1_CAN_TX},
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#endif /* CONFIG_CAN_1 */
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};
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static int pinmux_stm32_init(struct device *port)
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@ -313,6 +313,11 @@
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(STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_PULLUP)
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/* Port D */
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#define STM32F7_PINMUX_FUNC_PD0_CAN_RX \
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(STM32_PINMUX_ALT_FUNC_9 | STM32_PUPDR_PULL_UP)
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#define STM32F7_PINMUX_FUNC_PD1_CAN_TX \
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(STM32_PINMUX_ALT_FUNC_9 | STM32_PUSHPULL_NOPULL)
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#define STM32F7_PINMUX_FUNC_PD2_UART5_RX \
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(STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_NOPULL)
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@ -324,6 +324,18 @@
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label = "SPI_6";
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};
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can1: can@40006400 {
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compatible = "st,stm32-can";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40006400 0x400>;
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interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
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interrupt-names = "TX", "RX0", "RX1", "SCE";
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
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status = "disabled";
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label = "CAN_1";
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};
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timers1: timers@40010000 {
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compatible = "st,stm32-timers";
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reg = <0x40010000 0x400>;
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@ -371,5 +371,19 @@
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#define DT_FLASH_DEV_BASE_ADDRESS DT_ST_STM32F7_FLASH_CONTROLLER_40023C00_BASE_ADDRESS
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#define DT_FLASH_DEV_NAME DT_ST_STM32F7_FLASH_CONTROLLER_40023C00_LABEL
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#define DT_CAN_1_BASE_ADDRESS DT_ST_STM32_CAN_40006400_BASE_ADDRESS
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#define DT_CAN_1_BUS_SPEED DT_ST_STM32_CAN_40006400_BUS_SPEED
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#define DT_CAN_1_NAME DT_ST_STM32_CAN_40006400_LABEL
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#define DT_CAN_1_IRQ_TX DT_ST_STM32_CAN_40006400_IRQ_TX
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#define DT_CAN_1_IRQ_RX0 DT_ST_STM32_CAN_40006400_IRQ_RX0
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#define DT_CAN_1_IRQ_RX1 DT_ST_STM32_CAN_40006400_IRQ_RX1
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#define DT_CAN_1_IRQ_SCE DT_ST_STM32_CAN_40006400_IRQ_SCE
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#define DT_CAN_1_IRQ_PRIORITY DT_ST_STM32_CAN_40006400_IRQ_0_PRIORITY
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#define DT_CAN_1_SJW DT_ST_STM32_CAN_40006400_SJW
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#define DT_CAN_1_PROP_SEG_PHASE_SEG1 DT_ST_STM32_CAN_40006400_PROP_SEG_PHASE_SEG1
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#define DT_CAN_1_PHASE_SEG2 DT_ST_STM32_CAN_40006400_PHASE_SEG2
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#define DT_CAN_1_CLOCK_BUS DT_ST_STM32_CAN_40006400_CLOCK_BUS
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#define DT_CAN_1_CLOCK_BITS DT_ST_STM32_CAN_40006400_CLOCK_BITS
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#define DT_WDT_0_NAME DT_ST_STM32_WATCHDOG_0_LABEL
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/* End of SoC Level DTS fixup file */
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