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boards: arm: nucleo_f746zg: Activate CAN on nucleo F746zg

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This commit adds CAN support for nucleo F746zg.
Furtermore CAN was added in stm32f7.dtsi and pinmuc_stm32f7.h
CAN_RX: PD0, CAN_TX: PD1

Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
This commit is contained in:
Alexander Wachter 2019-04-05 13:54:59 +02:00 • committed by Anas Nashif
commit 78714b4ff4
6 changed files with 44 additions and 0 deletions
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8
boards/arm/nucleo_f746zg/nucleo_f746zg.dts
View file

@ -100,3 +100,11 @@ arduino_spi: &spi1 {};
&rtc { &rtc {
status = "ok"; status = "ok";
}; };
&can1 {
bus-speed = <125000>;
sjw = <1>;
prop_seg_phase_seg1 = <6>;
phase_seg2 = <5>;
status = "ok";
};

1
boards/arm/nucleo_f746zg/nucleo_f746zg.yaml
View file

@ -20,3 +20,4 @@ supported:
- watchdog - watchdog
- rtc - rtc
- counter - counter
- can

4
boards/arm/nucleo_f746zg/pinmux.c
View file

@ -62,6 +62,10 @@ static const struct pin_config pinconf[] = {
{ STM32_PIN_PA6, STM32F7_PINMUX_FUNC_PA6_SPI1_MISO }, { STM32_PIN_PA6, STM32F7_PINMUX_FUNC_PA6_SPI1_MISO },
{ STM32_PIN_PA7, STM32F7_PINMUX_FUNC_PA7_SPI1_MOSI }, { STM32_PIN_PA7, STM32F7_PINMUX_FUNC_PA7_SPI1_MOSI },
#endif /* CONFIG_SPI_1 */ #endif /* CONFIG_SPI_1 */
#ifdef CONFIG_CAN_1
{STM32_PIN_PD0, STM32F7_PINMUX_FUNC_PD0_CAN_RX},
{STM32_PIN_PD1, STM32F7_PINMUX_FUNC_PD1_CAN_TX},
#endif /* CONFIG_CAN_1 */
}; };
static int pinmux_stm32_init(struct device *port) static int pinmux_stm32_init(struct device *port)

5
drivers/pinmux/stm32/pinmux_stm32f7.h
View file

@ -313,6 +313,11 @@
(STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_PULLUP) (STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_PULLUP)
/* Port D */ /* Port D */
#define STM32F7_PINMUX_FUNC_PD0_CAN_RX \
(STM32_PINMUX_ALT_FUNC_9 | STM32_PUPDR_PULL_UP)
#define STM32F7_PINMUX_FUNC_PD1_CAN_TX \
(STM32_PINMUX_ALT_FUNC_9 | STM32_PUSHPULL_NOPULL)
#define STM32F7_PINMUX_FUNC_PD2_UART5_RX \ #define STM32F7_PINMUX_FUNC_PD2_UART5_RX \
(STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_NOPULL) (STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_NOPULL)

12
dts/arm/st/f7/stm32f7.dtsi
View file

@ -324,6 +324,18 @@
label = "SPI_6"; label = "SPI_6";
}; };
can1: can@40006400 {
compatible = "st,stm32-can";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40006400 0x400>;
interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
interrupt-names = "TX", "RX0", "RX1", "SCE";
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
status = "disabled";
label = "CAN_1";
};
timers1: timers@40010000 { timers1: timers@40010000 {
compatible = "st,stm32-timers"; compatible = "st,stm32-timers";
reg = <0x40010000 0x400>; reg = <0x40010000 0x400>;

14
soc/arm/st_stm32/stm32f7/dts_fixup.h
View file

@ -371,5 +371,19 @@
#define DT_FLASH_DEV_BASE_ADDRESS DT_ST_STM32F7_FLASH_CONTROLLER_40023C00_BASE_ADDRESS #define DT_FLASH_DEV_BASE_ADDRESS DT_ST_STM32F7_FLASH_CONTROLLER_40023C00_BASE_ADDRESS
#define DT_FLASH_DEV_NAME DT_ST_STM32F7_FLASH_CONTROLLER_40023C00_LABEL #define DT_FLASH_DEV_NAME DT_ST_STM32F7_FLASH_CONTROLLER_40023C00_LABEL
#define DT_CAN_1_BASE_ADDRESS DT_ST_STM32_CAN_40006400_BASE_ADDRESS
#define DT_CAN_1_BUS_SPEED DT_ST_STM32_CAN_40006400_BUS_SPEED
#define DT_CAN_1_NAME DT_ST_STM32_CAN_40006400_LABEL
#define DT_CAN_1_IRQ_TX DT_ST_STM32_CAN_40006400_IRQ_TX
#define DT_CAN_1_IRQ_RX0 DT_ST_STM32_CAN_40006400_IRQ_RX0
#define DT_CAN_1_IRQ_RX1 DT_ST_STM32_CAN_40006400_IRQ_RX1
#define DT_CAN_1_IRQ_SCE DT_ST_STM32_CAN_40006400_IRQ_SCE
#define DT_CAN_1_IRQ_PRIORITY DT_ST_STM32_CAN_40006400_IRQ_0_PRIORITY
#define DT_CAN_1_SJW DT_ST_STM32_CAN_40006400_SJW
#define DT_CAN_1_PROP_SEG_PHASE_SEG1 DT_ST_STM32_CAN_40006400_PROP_SEG_PHASE_SEG1
#define DT_CAN_1_PHASE_SEG2 DT_ST_STM32_CAN_40006400_PHASE_SEG2
#define DT_CAN_1_CLOCK_BUS DT_ST_STM32_CAN_40006400_CLOCK_BUS
#define DT_CAN_1_CLOCK_BITS DT_ST_STM32_CAN_40006400_CLOCK_BITS
#define DT_WDT_0_NAME DT_ST_STM32_WATCHDOG_0_LABEL #define DT_WDT_0_NAME DT_ST_STM32_WATCHDOG_0_LABEL
/* End of SoC Level DTS fixup file */ /* End of SoC Level DTS fixup file */