gpio: Add driver for Synopsys DesignWare GPIO devices
[DL: captilize commit message title; fixed some whitespaces;
changed the __initconfig_gpio_* from level 0 to level 1,
which is the level of pure_init; and added include path
to board.h; ]
Change-Id: I7eea6a6ca9e4b7cf8d1ccabb57f07f786da93ef0
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Dirk Brandewie
Anas Nashif
parent
1e39d6274b
commit
77a78f0827
7 changed files with 464 additions and 0 deletions
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@ -69,6 +69,26 @@ by x86 platforms.
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#endif /* CONFIG_IOAPIC */
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#endif /* CONFIG_UART_SIMPLE */
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#if defined(CONFIG_GPIO_DW)
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#if CONFIG_GPIO_DW_0
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#if defined(CONFIG_PIC)
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pic_master_mkstub gpio_dw_0 gpio_dw_isr_0
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#elif defined(CONFIG_IOAPIC)
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ioapic_mkstub gpio_dw_0 gpio_dw_isr_0
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#endif /* CONFIG_PIC */
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#endif /* CONFIG_GPIO_DW_0 */
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#if CONFIG_GPIO_DW_1
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#if defined(CONFIG_PIC)
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pic_master_mkstub gpio_dw_1 gpio_dw_isr_1
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#elif defined(CONFIG_IOAPIC)
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ioapic_mkstub gpio_dw_1 gpio_dw_isr_1
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#endif /* CONFIG_PIC */
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#endif /* CONFIG_GPIO_DW_1 */
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#endif /* CONFIG_GPIO_DW */
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#if defined(CONFIG_SPI_INTEL)
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#if defined(CONFIG_PIC)
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#if defined(CONFIG_SPI_INTEL_PORT_0)
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@ -41,6 +41,8 @@ source "drivers/console/Kconfig"
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source "drivers/serial/Kconfig"
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source "drivers/gpio/Kconfig"
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source "drivers/interrupt_controller/Kconfig"
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source "drivers/timer/Kconfig"
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@ -11,3 +11,4 @@ obj-$(CONFIG_PCI) += pci/
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obj-$(CONFIG_BLUETOOTH) += bluetooth/
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obj-$(CONFIG_UART_SIMPLE) += simple/
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obj-$(CONFIG_SPI) += spi/
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obj-$(CONFIG_GPIO) += gpio/
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87
drivers/gpio/Kconfig
Normal file
87
drivers/gpio/Kconfig
Normal file
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@ -0,0 +1,87 @@
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config GPIO_DW
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bool
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menuconfig GPIO
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bool
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prompt "GPIO Drivers"
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default n
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help
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Include GPIO drivers in system config
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config GPIO_DW_0
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bool "Designware GPIO block 0"
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depends on GPIO
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default n
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select GPIO_DW
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help
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Include Designware GPIO driver
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config GPIO_DW_0_NAME
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string "Driver name"
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depends on GPIO_DW_0
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default "GPIO_0"
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config GPIO_DW_0_BASE_ADDR
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hex "Controller base address"
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depends on GPIO_DW_0
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default 0x00000000
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config GPIO_DW_0_BITS
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int "number of pins controlled"
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depends on GPIO_DW_0
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default 32
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help
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Number of pins controlled by controller
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config GPIO_DW_0_IRQ
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int "Controller interrupt number"
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depends on GPIO_DW_0
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default 0
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help
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IRQ number for the controller
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config GPIO_DW_0_PRI
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int "Controller interrupt priority"
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depends on GPIO_DW_0
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default 0
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help
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IRQ priority
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config GPIO_DW_1
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bool "Designware GPIO block 1"
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depends on GPIO
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select GPIO_DW
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default n
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help
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Include Designware GPIO driver
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config GPIO_DW_1_NAME
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string "Driver name"
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depends on GPIO_DW_1
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default "GPIO_1"
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config GPIO_DW_1_BASE_ADDR
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hex "Controller base address"
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depends on GPIO_DW_1
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default 0x00000000
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config GPIO_DW_1_BITS
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int "number of pins controlled"
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depends on GPIO_DW_1
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default 32
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help
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Number of pins controlled by controller
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config GPIO_DW_1_IRQ
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int "Controller interrupt number"
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depends on GPIO_DW_1
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default 0
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help
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IRQ number for the controller
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config GPIO_DW_1_PRI
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int "Controller interrupt priority"
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depends on GPIO_DW_1
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default 0
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help
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IRQ priority
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3
drivers/gpio/Makefile
Normal file
3
drivers/gpio/Makefile
Normal file
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@ -0,0 +1,3 @@
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ccflags-y +=-I$(srctree)/drivers
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obj-$(CONFIG_GPIO_DW) = gpio-dw.o
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302
drivers/gpio/gpio-dw.c
Normal file
302
drivers/gpio/gpio-dw.c
Normal file
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@ -0,0 +1,302 @@
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/*
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* Copyright (c) 2015 Intel Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <nanokernel.h>
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#include <gpio.h>
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#include <gpio/gpio-dw.h>
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#include <board.h>
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#define SWPORTA_DR 0x00
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#define SWPORTA_DDR 0x04
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#define SWPORTB_DR 0x0c
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#define SWPORTB_DDR 0x10
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#define SWPORTC_DR 0x18
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#define SWPORTC_DDR 0x1c
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#define SWPORTD_DR 0x24
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#define SWPORTD_DDR 0x28
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#define INTEN 0x30
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#define INTMASK 0x34
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#define INTTYPE_LEVEL 0x38
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#define INT_POLARITY 0x3c
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#define INTSTATUS 0x40
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#define PORTA_DEBOUNCE 0x48
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#define PORTA_EOI 0x4c
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#define EXT_PORTA 0x50
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#define EXT_PORTB 0x54
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#define EXT_PORTC 0x58
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#define EXT_PORTD 0x5c
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#define INT_CLOCK_SYNC 0x60
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#define INT_BOTHEDGE 0x68
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#define BIT(n) (1UL << (n))
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static inline uint32_t dw_read(uint32_t base_addr, uint32_t offest)
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{
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return *(uint32_t*)(base_addr+offest);
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}
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static inline void dw_write(uint32_t base_addr, uint32_t offest,
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uint32_t val)
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{
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*(uint32_t*)(base_addr+offest) = val;
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}
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static void dw_set_bit(uint32_t base_addr, uint32_t offset,
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uint32_t bit, uint8_t value)
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{
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uint32_t reg;
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reg = dw_read(base_addr, offset);
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reg &= ~BIT(bit);
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reg |= ((value & 0x1) << bit);
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dw_write(base_addr, offset, reg);
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}
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static inline void dw_interrupt_config(struct device *port, int access_op,
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uint32_t pin, int flags)
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{
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struct gpio_config_dw *config = port->config->config_info;
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uint32_t base_addr = config->base_addr;
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uint8_t flag_is_set;
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/* set as an input pin */
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dw_set_bit(base_addr, SWPORTA_DDR, pin, 0);
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/* level or edge */
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flag_is_set = (flags & GPIO_INT_EDGE);
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dw_set_bit(base_addr, INTTYPE_LEVEL, pin, flag_is_set);
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/* Active low/high */
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flag_is_set = (flags & GPIO_INT_ACTIVE_HIGH);
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dw_set_bit(base_addr, INT_POLARITY, pin, flag_is_set);
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/* both edges */
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flag_is_set = (flags & GPIO_INT_DOUBLE_EDGE);
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if (flag_is_set) {
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dw_set_bit(base_addr, INT_BOTHEDGE, pin, flag_is_set);
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dw_set_bit(base_addr, INTTYPE_LEVEL, pin, flag_is_set);
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}
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/* use built-in debounce */
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flag_is_set = (flags & GPIO_INT_DEBOUNCE );
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dw_set_bit(base_addr, PORTA_DEBOUNCE, pin, flag_is_set);
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/* level triggered int synchronous with clock */
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flag_is_set = (flags & GPIO_INT_CLOCK_SYNC );
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dw_set_bit(base_addr, INT_CLOCK_SYNC, pin, flag_is_set);
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dw_set_bit(base_addr, INTEN, pin, 1);
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}
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static inline void dw_pin_config(struct device *port,
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uint32_t pin, int flags)
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{
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struct gpio_config_dw *config = port->config->config_info;
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uint32_t base_addr = config->base_addr;
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/* clear interrupt enable */
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dw_set_bit(base_addr, INTEN, pin, 0);
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/* set direction */
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dw_set_bit(base_addr, SWPORTA_DDR, pin, (flags & GPIO_DIR_MASK));
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if (flags & GPIO_INT)
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dw_interrupt_config(port, GPIO_ACCESS_BY_PIN, pin, flags);
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}
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static inline void dw_port_config(struct device *port, int flags)
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{
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struct gpio_config_dw *config = port->config->config_info;
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int i;
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for (i=0; i < config->bits; i++) {
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dw_pin_config(port, i, flags);
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}
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}
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static inline int gpio_config_dw(struct device *port, int access_op,
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uint32_t pin, int flags)
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{
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if (((flags & GPIO_INT) && (flags & GPIO_DIR_OUT)) ||
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((flags & GPIO_DIR_IN) && (flags & GPIO_DIR_OUT))) {
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return -1;
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}
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if (GPIO_ACCESS_BY_PIN == access_op) {
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dw_pin_config(port, pin, flags);
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} else {
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dw_port_config(port, flags);
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}
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return 0;
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}
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static inline int gpio_write_dw(struct device *port, int access_op,
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uint32_t pin, uint32_t value)
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{
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struct gpio_config_dw *config = port->config->config_info;
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uint32_t base_addr = config->base_addr;
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if (GPIO_ACCESS_BY_PIN == access_op) {
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dw_set_bit(base_addr, SWPORTA_DR, pin, value);
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} else {
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dw_write(base_addr, SWPORTA_DR, value);
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}
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return 0;
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}
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static inline int gpio_read_dw(struct device *port, int access_op,
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uint32_t pin, uint32_t *value)
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{
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struct gpio_config_dw *config = port->config->config_info;
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uint32_t base_addr = config->base_addr;
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*value = dw_read(base_addr, EXT_PORTA);
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if (GPIO_ACCESS_BY_PIN == access_op) {
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*value = !!(*value & BIT(pin));
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}
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return 0;
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}
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static inline int gpio_set_callback_dw(struct device *port,
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gpio_callback_t callback)
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{
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struct gpio_runtime_dw *context = port->driver_data;
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context->callback = callback;
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return 0;
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}
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static inline int gpio_enable_callback_dw(struct device *port, int access_op,
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uint32_t pin)
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{
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struct gpio_config_dw *config = port->config->config_info;
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struct gpio_runtime_dw *context = port->driver_data;
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uint32_t base_addr = config->base_addr;
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if (GPIO_ACCESS_BY_PIN == access_op) {
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context->enabled_callbacks |= BIT(pin);
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} else {
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context->port_callback = 1;
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}
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dw_write(base_addr, PORTA_EOI, BIT(pin));
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dw_set_bit(base_addr, INTMASK, pin, 0);
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return 0;
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}
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static inline int gpio_disable_callback_dw(struct device *port, int access_op,
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uint32_t pin)
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{
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struct gpio_config_dw *config = port->config->config_info;
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struct gpio_runtime_dw *context = port->driver_data;
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uint32_t base_addr = config->base_addr;
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if (GPIO_ACCESS_BY_PIN == access_op) {
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context->enabled_callbacks &= ~(BIT(pin));
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} else {
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context->port_callback = 0;
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}
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dw_set_bit(base_addr, INTMASK, pin, 1);
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return 0;
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}
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static inline int gpio_suspend_port_dw(struct device *port)
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{
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return 0;
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}
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static inline int gpio_resume_port_dw(struct device *port)
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{
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return 0;
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}
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void gpio_dw_isr(struct device *port)
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{
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struct gpio_runtime_dw *context = port->driver_data;
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struct gpio_config_dw *config = port->config->config_info;
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uint32_t base_addr = config->base_addr;
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uint32_t int_status, bit;
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int_status = dw_read(base_addr, INTSTATUS);
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dw_write(base_addr, PORTA_EOI, -1);
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if (!context->callback) {
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return;
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}
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if (context->port_callback) {
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context->callback(port, int_status);
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return;
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}
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if (context->enabled_callbacks) {
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for (bit = 0; bit < 32; bit++) {
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if (context->enabled_callbacks & (1 << bit)) {
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context->callback(port, (1 << bit));
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}
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}
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}
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}
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struct gpio_driver_api api_funcs = {
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.config = gpio_config_dw,
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.write = gpio_write_dw,
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.read = gpio_read_dw,
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.set_callback = gpio_set_callback_dw,
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.enable_callback = gpio_enable_callback_dw,
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.disable_callback = gpio_disable_callback_dw,
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.suspend = gpio_suspend_port_dw,
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.resume = gpio_resume_port_dw
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};
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int gpio_initialize_dw(struct device *port)
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{
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struct gpio_config_dw *config = port->config->config_info;
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uint32_t base_addr = config->base_addr;
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/* interrupts in sync with system clock */
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dw_set_bit(base_addr, INT_CLOCK_SYNC, 0, 1);
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/* mask and disable interrupts */
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dw_write(base_addr, INTMASK, ~(0));
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dw_write(base_addr, INTEN, 0);
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dw_write(base_addr, PORTA_EOI, ~(0));
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port->driver_api = &api_funcs;
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config->config_func(port);
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irq_enable(config->irq_num);
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return 0;
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}
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49
drivers/gpio/gpio-dw.h
Normal file
49
drivers/gpio/gpio-dw.h
Normal file
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@ -0,0 +1,49 @@
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/*
|
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* Copyright (c) 2015 Intel Corporation.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1) Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2) Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3) Neither the name of Intel Corporation nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software without
|
||||
* specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <gpio.h>
|
||||
|
||||
#define CONFIG_GPIO_DW_BITS 32
|
||||
extern int gpio_initialize_dw(struct device *port);
|
||||
typedef void (*gpio_config_irq_t)(struct device *port);
|
||||
|
||||
struct gpio_config_dw {
|
||||
uint32_t base_addr;
|
||||
uint32_t bits;
|
||||
uint32_t irq_num;
|
||||
gpio_config_irq_t config_func;
|
||||
};
|
||||
|
||||
struct gpio_runtime_dw {
|
||||
gpio_callback_t callback;
|
||||
uint32_t enabled_callbacks;
|
||||
uint8_t port_callback;
|
||||
};
|
||||
Loading…
Add table
Add a link
Reference in a new issue