boards: nucleo_f401re: add new board

Add configuration for Nucleo-64 F410RE board.

Change-Id: I88b06d87f0fc62b941241cc2f374b8541de86e00
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>

MAINTAINERS

@@ -120,6 +120,12 @@ M:	Carles Cufi <carles.cufi@nordicsemi.no>
 S:	Supported
 F:	boards/arm/nrf52_pca10040/
 
+BOARDS/ARM - NUCLEO-64 F401RE Devboard
+M:	Amit Kucheria <amit.kucheria@linaro.org>
+M:	Ricardo Salveti <ricardo.salveti@linaro.org>
+S:	Supported
+F:	boards/arm/nucleo_f401re/
+
 BOARDS/NIOS2 - ALTERA MAX10
 M:	Andrew Boie <andrew.p.boie@intel.com>
 S:	Supported

boards/arm/nucleo_f401re/Kconfig.board

@@ -0,0 +1,20 @@
+# Kconfig - NUCLEO-64 F401RE board configuration
+#
+# Copyright (c) 2016 Linaro Limited.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+config BOARD_NUCLEO_F401RE
+	bool "NUCLEO-64 F401RE Development Board"
+	depends on SOC_STM32F401RE

boards/arm/nucleo_f401re/Kconfig.defconfig

@@ -0,0 +1,23 @@
+# Kconfig - NUCLEO-64 F401RE board configuration
+#
+# Copyright (c) 2016 Linaro Limited.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+if BOARD_NUCLEO_F401RE
+
+config BOARD
+	default nucleo_f401re
+
+endif # BOARD_NUCLEO_F401RE

boards/arm/nucleo_f401re/Makefile

@@ -0,0 +1,2 @@
+# No C files (yet)
+obj- += dummy.o

boards/arm/nucleo_f401re/Makefile.board

@@ -0,0 +1,6 @@
+FLASH_SCRIPT = openocd.sh
+
+OPENOCD_LOAD_CMD = "flash write_image erase ${O}/${KERNEL_BIN_NAME} ${CONFIG_FLASH_BASE_ADDRESS}"
+OPENOCD_VERIFY_CMD = "verify_image ${O}/${KERNEL_BIN_NAME} ${CONFIG_FLASH_BASE_ADDRESS}"
+
+export FLASH_SCRIPT OPENOCD_LOAD_CMD OPENOCD_VERIFY_CMD

boards/arm/nucleo_f401re/board.h

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2016 Linaro Limited.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __INC_BOARD_H
+#define __INC_BOARD_H
+
+#include <soc.h>
+
+#endif /* __INC_BOARD_H */

boards/arm/nucleo_f401re/nucleo_f401re_defconfig

@@ -0,0 +1,48 @@
+CONFIG_ARM=y
+CONFIG_BOARD_NUCLEO_F401RE=y
+CONFIG_SOC_FAMILY_STM32=y
+CONFIG_SOC_SERIES_STM32F4X=y
+CONFIG_SOC_STM32F401RE=y
+# 84MHz system clock
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=84000000
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
+
+# enable uart driver
+CONFIG_SERIAL=y
+CONFIG_UART_STM32=y
+# enable USART2 - passthrough to STLINK v2 connector
+CONFIG_UART_STM32_PORT_1=y
+CONFIG_UART_STM32_PORT_1_BAUD_RATE=115200
+# enable console on this port by default
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_UART_CONSOLE_ON_DEV_NAME="UART_1"
+
+# enable pinmux
+CONFIG_PINMUX=y
+CONFIG_PINMUX_STM32=y
+
+# enable GPIO ports A, B, C
+CONFIG_GPIO=y
+CONFIG_GPIO_STM32=y
+CONFIG_GPIO_STM32_PORTA=y
+CONFIG_GPIO_STM32_PORTB=y
+CONFIG_GPIO_STM32_PORTC=y
+
+# clock configuration
+CONFIG_CLOCK_CONTROL=y
+CONFIG_CLOCK_CONTROL_STM32F4X=y
+CONFIG_CLOCK_STM32F4X_SYSCLK_SRC_PLL=y
+# use HSE as PLL input
+CONFIG_CLOCK_STM32F4X_PLL_SRC_HSE=y
+# however, the board does not have an external oscillator, so just use
+# the 8MHz clock signal coming from integrated STLink
+CONFIG_CLOCK_STM32F4X_HSE_BYPASS=y
+# produce 84MHz clock at PLL output
+CONFIG_CLOCK_STM32F4X_PLLM_DIV_FACTOR=8
+CONFIG_CLOCK_STM32F4X_PLLN_MULTIPLIER=336
+CONFIG_CLOCK_STM32F4X_PLLP_DIV_FACTOR=4
+CONFIG_CLOCK_STM32F4X_PLLQ_DIV_FACTOR=7
+CONFIG_CLOCK_STM32F4X_AHB_PRESCALER=0
+CONFIG_CLOCK_STM32F4X_APB1_PRESCALER=2
+CONFIG_CLOCK_STM32F4X_APB2_PRESCALER=0

boards/arm/nucleo_f401re/support/openocd.cfg

@@ -0,0 +1,12 @@
+source [find board/st_nucleo_f4.cfg]
+
+$_TARGETNAME configure -event gdb-attach {
+	echo "Debugger attaching: halting execution"
+	reset halt
+	gdb_breakpoint_override hard
+}
+
+$_TARGETNAME configure -event gdb-detach {
+	echo "Debugger detaching: resuming execution"
+	resume
+}

drivers/pinmux/Makefile

@@ -6,6 +6,7 @@ obj-$(CONFIG_BOARD_FRDM_K64F) += k64/pinmux_board_frdm_k64f.o
 obj-$(CONFIG_BOARD_HEXIWEAR_K64) += k64/pinmux_board_hexiwear.o
 obj-$(CONFIG_PINMUX_STM32) += stm32/pinmux_stm32.o
 obj-$(CONFIG_BOARD_NUCLEO_F103RB) += stm32/pinmux_board_nucleo_f103rb.o
+obj-$(CONFIG_BOARD_NUCLEO_F401RE) += stm32/pinmux_board_nucleo_f401re.o
 obj-$(CONFIG_BOARD_OLIMEXINO_STM32) += stm32/pinmux_board_olimexino_stm32.o
 obj-$(CONFIG_BOARD_STM32_MINI_A15) += stm32/pinmux_board_stm32_mini_a15.o
 

drivers/pinmux/stm32/pinmux_board_nucleo_f401re.c

@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2016 Linaro Limited.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <nanokernel.h>
+#include <device.h>
+#include <init.h>
+#include <pinmux.h>
+#include <sys_io.h>
+#include "pinmux/pinmux.h"
+
+#include "pinmux_stm32.h"
+
+/* pin assignments for NUCLEO-F401RE board */
+static const struct pin_config pinconf[] = {
+#ifdef CONFIG_UART_STM32_PORT_0
+	{STM32_PIN_PB6, STM32F4_PINMUX_FUNC_PB6_USART1_TX},
+	{STM32_PIN_PB7, STM32F4_PINMUX_FUNC_PB7_USART1_RX},
+#endif	/* CONFIG_UART_STM32_PORT_0 */
+#ifdef CONFIG_UART_STM32_PORT_1
+	{STM32_PIN_PA2, STM32F4_PINMUX_FUNC_PA2_USART2_TX},
+	{STM32_PIN_PA3, STM32F4_PINMUX_FUNC_PA3_USART2_RX},
+#endif	/* CONFIG_UART_STM32_PORT_1 */
+};
+
+static int pinmux_stm32_init(struct device *port)
+{
+	ARG_UNUSED(port);
+
+	stm32_setup_pins(pinconf, ARRAY_SIZE(pinconf));
+
+	return 0;
+}
+
+SYS_INIT(pinmux_stm32_init, PRIMARY,
+		CONFIG_PINMUX_STM32_DEVICE_INITIALIZATION_PRIORITY);

scripts/sanity_chk/arches/arm.ini

@@ -2,7 +2,7 @@
 name = arm
 platforms = qemu_cortex_m3 frdm_k64f arduino_due nucleo_f103rb stm32_mini_a15
             olimexino_stm32 96b_nitrogen nrf52_pca10040 hexiwear_k64
-            nrf51_pca10028 arduino_101_ble
+            nrf51_pca10028 arduino_101_ble nucleo_f401re
 supported_toolchains = zephyr gccarmemb
 
 [qemu_cortex_m3]