drivers/interrupt_controller: stm32: add support of stm32mp1

Add support of the stm32mp1 gpio exti.

Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>

drivers/interrupt_controller/Kconfig.stm32

@@ -74,6 +74,87 @@ config EXTI_STM32_EXTI4_IRQ_PRI
 	help
 	 IRQ priority of EXTI4 interrupt
 
+if SOC_SERIES_STM32MP1X
+config EXTI_STM32_EXTI5_IRQ_PRI
+	int "EXTI5 IRQ priority"
+	depends on EXTI_STM32
+	default 0
+	help
+	 IRQ priority of EXTI5 interrupt
+
+config EXTI_STM32_EXTI6_IRQ_PRI
+	int "EXTI6 IRQ priority"
+	depends on EXTI_STM32
+	default 0
+	help
+	 IRQ priority of EXTI6 interrupt
+
+config EXTI_STM32_EXTI7_IRQ_PRI
+	int "EXTI7 IRQ priority"
+	depends on EXTI_STM32
+	default 0
+	help
+	 IRQ priority of EXTI7 interrupt
+
+config EXTI_STM32_EXTI8_IRQ_PRI
+	int "EXTI8 IRQ priority"
+	depends on EXTI_STM32
+	default 0
+	help
+	 IRQ priority of EXTI8 interrupt
+
+config EXTI_STM32_EXTI9_IRQ_PRI
+	int "EXTI9 IRQ priority"
+	depends on EXTI_STM32
+	default 0
+	help
+	 IRQ priority of EXTI9 interrupt
+
+config EXTI_STM32_EXTI10_IRQ_PRI
+	int "EXTI10 IRQ priority"
+	depends on EXTI_STM32
+	default 0
+	help
+	 IRQ priority of EXTI10 interrupt
+
+config EXTI_STM32_EXTI11_IRQ_PRI
+	int "EXTI11 IRQ priority"
+	depends on EXTI_STM32
+	default 0
+	help
+	 IRQ priority of EXTI11 interrupt
+
+config EXTI_STM32_EXTI12_IRQ_PRI
+	int "EXTI12 IRQ priority"
+	depends on EXTI_STM32
+	default 0
+	help
+	 IRQ priority of EXTI12 interrupt
+
+config EXTI_STM32_EXTI13_IRQ_PRI
+	int "EXTI13 IRQ priority"
+	depends on EXTI_STM32
+	default 0
+	help
+	 IRQ priority of EXTI13 interrupt
+
+config EXTI_STM32_EXTI14_IRQ_PRI
+	int "EXTI14 IRQ priority"
+	depends on EXTI_STM32
+	default 0
+	help
+	 IRQ priority of EXTI14 interrupt
+
+config EXTI_STM32_EXTI15_IRQ_PRI
+	int "EXTI15 IRQ priority"
+	depends on EXTI_STM32
+	default 0
+	help
+	 IRQ priority of EXTI15 interrupt
+
+endif # SOC_SERIES_STM32MP1X
+
+if SOC_SERIES_STM32MP1X!=y
 config EXTI_STM32_EXTI9_5_IRQ_PRI
 	int "EXTI9:5 IRQ priority"
 	depends on EXTI_STM32
@@ -87,6 +168,7 @@ config EXTI_STM32_EXTI15_10_IRQ_PRI
 	default 0
 	help
 	 IRQ priority of EXTI15:10 interrupt
+endif # SOC_SERIES_STM32MP1X!=y
 
 endif # SOC_SERIES_STM32F0X!=y && SOC_SERIES_STM32L0X!=y
 

drivers/interrupt_controller/exti_stm32.c

@@ -43,6 +43,31 @@
 #define EXTI_LINES 30
 #elif defined(CONFIG_SOC_SERIES_STM32L4X)
 #define EXTI_LINES 40
+#elif defined(CONFIG_SOC_SERIES_STM32MP1X)
+#define EXTI_LINES 76
+#endif
+
+#if defined(CONFIG_SOC_SERIES_STM32MP1X)
+IRQn_Type exti_irq_table[] = {
+	EXTI0_IRQn, EXTI1_IRQn, EXTI2_IRQn, EXTI3_IRQn,
+	EXTI4_IRQn, EXTI5_IRQn, EXTI6_IRQn, EXTI7_IRQn,
+	EXTI8_IRQn, EXTI9_IRQn, EXTI10_IRQn, EXTI11_IRQn,
+	EXTI12_IRQn, EXTI13_IRQn, EXTI14_IRQn, EXTI15_IRQn,
+	PVD_AVD_IRQn, RTC_TIMESTAMP_IRQn, TAMP_IRQn, RTC_WKUP_ALARM_IRQn,
+	0xFF, I2C1_EV_IRQn, I2C2_EV_IRQn, I2C3_EV_IRQn,
+	I2C3_EV_IRQn, I2C5_EV_IRQn, USART1_IRQn, USART2_IRQn,
+	USART3_IRQn, USART6_IRQn, UART4_IRQn, UART5_IRQn,
+	UART7_IRQn, UART8_IRQn, 0xFF, 0xFF,
+	SPI1_IRQn, SPI2_IRQn, SPI3_IRQn, SPI4_IRQn,
+	SPI5_IRQn, SPI6_IRQn, MDIOS_IRQn, USBH_OHCI_IRQn,
+	OTG_IRQn, 0xFF, 0xFF, LPTIM1_IRQn,
+	LPTIM2_IRQn, 0xFF, LPTIM3_IRQn, 0xFF,
+	LPTIM4_IRQn, LPTIM5_IRQn, I2C6_EV_IRQn, WAKEUP_PIN_IRQn,
+	WAKEUP_PIN_IRQn, WAKEUP_PIN_IRQn, WAKEUP_PIN_IRQn, WAKEUP_PIN_IRQn,
+	WAKEUP_PIN_IRQn, IPCC_RX0_IRQn, IPCC_RX1_IRQn, 0xFF,
+	0xFF, 0xFF, 0xFF, 0xFF,
+	0xFF, CEC_IRQn, ETH1_WKUP_IRQn, 0xFF, DTS_IRQn
+};
 #endif
 
 /* wrapper for user callback */
@@ -63,11 +88,17 @@ int stm32_exti_enable(int line)
 
 	if (line < 32) {
 		LL_EXTI_EnableIT_0_31(1 << line);
-	} else {
+	} else if (line < 64) {
 #if EXTI_LINES > 32
 		LL_EXTI_EnableIT_32_63(1 << (line - 32));
 #else
 		__ASSERT_NO_MSG(line);
+#endif
+	} else {
+#if EXTI_LINES > 64
+		LL_EXTI_EnableIT_64_95(1 << (line - 32));
+#else
+		__ASSERT_NO_MSG(line);
 #endif
 	}
 
@@ -141,6 +172,14 @@ int stm32_exti_enable(int line)
 #endif /* CONFIG_SOC_SERIES_STM32L4X */
 		}
 	}
+#elif defined(CONFIG_SOC_SERIES_STM32MP1X)
+	if (line <= 72) {
+		irqnum = exti_irq_table[line];
+		if (irqnum == 0xFF)
+			return 0;
+	} else {
+		return -ENOTSUP;
+	}
 #else
 	#error "Unknown STM32 SoC"
 #endif
@@ -154,11 +193,17 @@ void stm32_exti_disable(int line)
 {
 	if (line < 32) {
 		LL_EXTI_DisableIT_0_31(1 << line);
-	} else {
+	} else if (line < 64) {
 #if EXTI_LINES > 32
 		LL_EXTI_DisableIT_32_63(1 << (line - 32));
 #else
 		__ASSERT_NO_MSG(line);
+#endif
+	} else {
+#if EXTI_LINES > 64
+		LL_EXTI_DisableIT_64_95(1 << (line - 64));
+#else
+		__ASSERT_NO_MSG(line);
 #endif
 	}
 }
@@ -171,10 +216,32 @@ void stm32_exti_disable(int line)
 static inline int stm32_exti_is_pending(int line)
 {
 	if (line < 32) {
+#if defined(CONFIG_SOC_SERIES_STM32MP1X)
+		return (LL_EXTI_IsActiveRisingFlag_0_31(1 << line) ||
+			LL_EXTI_IsActiveFallingFlag_0_31(1 << line));
+#else
 		return LL_EXTI_IsActiveFlag_0_31(1 << line);
-	} else {
+#endif
+	} else if (line < 64) {
 #if EXTI_LINES > 32
+#if defined(CONFIG_SOC_SERIES_STM32MP1X)
+		__ASSERT_NO_MSG(line);
+		return 0;
+#else
 		return LL_EXTI_IsActiveFlag_32_63(1 << (line - 32));
+#endif
+#else
+		__ASSERT_NO_MSG(line);
+		return 0;
+#endif
+	} else {
+#if EXTI_LINES > 64
+#if defined(CONFIG_SOC_SERIES_STM32MP1X)
+		return (LL_EXTI_IsActiveRisingFlag_64_95(1 << (line - 64)) ||
+			LL_EXTI_IsActiveFallingFlag_64_95(1 << (line - 64)));
+#else
+		return LL_EXTI_IsActiveFlag_64_96(1 << (line - 64));
+#endif
 #else
 		__ASSERT_NO_MSG(line);
 		return 0;
@@ -190,10 +257,28 @@ static inline int stm32_exti_is_pending(int line)
 static inline void stm32_exti_clear_pending(int line)
 {
 	if (line < 32) {
+#if defined(CONFIG_SOC_SERIES_STM32MP1X)
+		LL_EXTI_ClearRisingFlag_0_31(1 << line);
+		LL_EXTI_ClearFallingFlag_0_31(1 << line);
+#else
 		LL_EXTI_ClearFlag_0_31(1 << line);
-	} else {
+#endif
+	} else if (line < 64) {
 #if EXTI_LINES > 32
+#if !defined(CONFIG_SOC_SERIES_STM32MP1X)
 		LL_EXTI_ClearFlag_32_63(1 << (line - 32));
+#endif
+#else
+		__ASSERT_NO_MSG(line);
+#endif
+	} else {
+#if EXTI_LINES > 64
+#if defined(CONFIG_SOC_SERIES_STM32MP1X)
+		LL_EXTI_ClearRisingFlag_64_95(1 << (line - 64));
+		LL_EXTI_ClearFallingFlag_64_95(1 << (line - 64));
+#else
+		__ASSERT_NO_MSG(line);
+#endif
 #else
 		__ASSERT_NO_MSG(line);
 #endif
@@ -205,11 +290,23 @@ void stm32_exti_trigger(int line, int trigger)
 	if (trigger & STM32_EXTI_TRIG_RISING) {
 		if (line < 32) {
 			LL_EXTI_EnableRisingTrig_0_31(1 << line);
-		} else {
+		} else  if (line < 64) {
 #if EXTI_LINES > 32
+#if defined(CONFIG_SOC_SERIES_STM32MP1X)
+			__ASSERT_NO_MSG(line);
+#else
 			LL_EXTI_EnableRisingTrig_32_63(1 << (line - 32));
+#endif
 #else
 			__ASSERT_NO_MSG(line);
+#endif
+		} else {
+#if EXTI_LINES > 64
+#if !defined(CONFIG_SOC_SERIES_STM32MP1X)
+			__ASSERT_NO_MSG(line);
+#else
+			LL_EXTI_EnableRisingTrig_64_95(1 << (line - 64));
+#endif
 #endif
 		}
 	}
@@ -217,11 +314,23 @@ void stm32_exti_trigger(int line, int trigger)
 	if (trigger & STM32_EXTI_TRIG_FALLING) {
 		if (line < 32) {
 			LL_EXTI_EnableFallingTrig_0_31(1 << line);
-		} else {
+		} else if (line < 64) {
 #if EXTI_LINES > 32
+#if defined(CONFIG_SOC_SERIES_STM32MP1X)
+			__ASSERT_NO_MSG(line);
+#else
 			LL_EXTI_EnableFallingTrig_32_63(1 << (line - 32));
+#endif
 #else
 			__ASSERT_NO_MSG(line);
+#endif
+		} else {
+#if EXTI_LINES > 64
+#if !defined(CONFIG_SOC_SERIES_STM32MP1X)
+			__ASSERT_NO_MSG(line);
+#else
+			LL_EXTI_EnableRisingTrig_64_95(1 << (line - 64));
+#endif
 #endif
 		}
 	}
@@ -301,6 +410,63 @@ static inline void __stm32_exti_isr_4(void *arg)
 	__stm32_exti_isr(4, 5, arg);
 }
 
+#if defined(CONFIG_SOC_SERIES_STM32MP1X)
+static inline void __stm32_exti_isr_5(void *arg)
+{
+	__stm32_exti_isr(5, 6, arg);
+}
+
+static inline void __stm32_exti_isr_6(void *arg)
+{
+	__stm32_exti_isr(6, 7, arg);
+}
+
+static inline void __stm32_exti_isr_7(void *arg)
+{
+	__stm32_exti_isr(7, 8, arg);
+}
+
+static inline void __stm32_exti_isr_8(void *arg)
+{
+	__stm32_exti_isr(8, 9, arg);
+}
+
+static inline void __stm32_exti_isr_9(void *arg)
+{
+	__stm32_exti_isr(9, 10, arg);
+}
+
+static inline void __stm32_exti_isr_10(void *arg)
+{
+	__stm32_exti_isr(10, 11, arg);
+}
+
+static inline void __stm32_exti_isr_11(void *arg)
+{
+	__stm32_exti_isr(11, 12, arg);
+}
+
+static inline void __stm32_exti_isr_12(void *arg)
+{
+	__stm32_exti_isr(12, 13, arg);
+}
+
+static inline void __stm32_exti_isr_13(void *arg)
+{
+	__stm32_exti_isr(13, 14, arg);
+}
+
+static inline void __stm32_exti_isr_14(void *arg)
+{
+	__stm32_exti_isr(14, 15, arg);
+}
+
+static inline void __stm32_exti_isr_15(void *arg)
+{
+	__stm32_exti_isr(15, 16, arg);
+}
+#endif
+
 static inline void __stm32_exti_isr_9_5(void *arg)
 {
 	__stm32_exti_isr(5, 10, arg);
@@ -313,7 +479,8 @@ static inline void __stm32_exti_isr_15_10(void *arg)
 
 #if defined(CONFIG_SOC_SERIES_STM32F4X) || \
 	defined(CONFIG_SOC_SERIES_STM32F7X) || \
-	defined(CONFIG_SOC_SERIES_STM32F2X)
+	defined(CONFIG_SOC_SERIES_STM32F2X) || \
+	defined(CONFIG_SOC_SERIES_STM32MP1X)
 static inline void __stm32_exti_isr_16(void *arg)
 {
 	__stm32_exti_isr(16, 17, arg);
@@ -334,12 +501,13 @@ static inline void __stm32_exti_isr_22(void *arg)
 	__stm32_exti_isr(22, 23, arg);
 }
 #endif
-#ifdef CONFIG_SOC_SERIES_STM32F7X
+#if defined(CONFIG_SOC_SERIES_STM32F7X) || \
+	defined(CONFIG_SOC_SERIES_STM32MP1X)
 static inline void __stm32_exti_isr_23(void *arg)
 {
 	__stm32_exti_isr(23, 24, arg);
 }
-#endif /* CONFIG_SOC_SERIES_STM32F7X */
+#endif
 #endif /* CONFIG_SOC_SERIES_STM32F0X */
 
 static void __stm32_exti_connect_irqs(struct device *dev);
@@ -413,7 +581,8 @@ static void __stm32_exti_connect_irqs(struct device *dev)
       defined(CONFIG_SOC_SERIES_STM32F3X) || \
       defined(CONFIG_SOC_SERIES_STM32F4X) || \
       defined(CONFIG_SOC_SERIES_STM32F7X) || \
-      defined(CONFIG_SOC_SERIES_STM32L4X)
+      defined(CONFIG_SOC_SERIES_STM32L4X) || \
+      defined(CONFIG_SOC_SERIES_STM32MP1X)
 	IRQ_CONNECT(EXTI0_IRQn,
 		CONFIG_EXTI_STM32_EXTI0_IRQ_PRI,
 		__stm32_exti_isr_0, DEVICE_GET(exti_stm32),
@@ -441,6 +610,7 @@ static void __stm32_exti_connect_irqs(struct device *dev)
 		CONFIG_EXTI_STM32_EXTI4_IRQ_PRI,
 		__stm32_exti_isr_4, DEVICE_GET(exti_stm32),
 		0);
+#ifndef CONFIG_SOC_SERIES_STM32MP1X
 	IRQ_CONNECT(EXTI9_5_IRQn,
 		CONFIG_EXTI_STM32_EXTI9_5_IRQ_PRI,
 		__stm32_exti_isr_9_5, DEVICE_GET(exti_stm32),
@@ -449,6 +619,53 @@ static void __stm32_exti_connect_irqs(struct device *dev)
 		CONFIG_EXTI_STM32_EXTI15_10_IRQ_PRI,
 		__stm32_exti_isr_15_10, DEVICE_GET(exti_stm32),
 		0);
+#else
+	IRQ_CONNECT(EXTI5_IRQn,
+		CONFIG_EXTI_STM32_EXTI5_IRQ_PRI,
+		__stm32_exti_isr_5, DEVICE_GET(exti_stm32),
+		0);
+	IRQ_CONNECT(EXTI6_IRQn,
+		CONFIG_EXTI_STM32_EXTI6_IRQ_PRI,
+		__stm32_exti_isr_6, DEVICE_GET(exti_stm32),
+		0);
+	IRQ_CONNECT(EXTI7_IRQn,
+		CONFIG_EXTI_STM32_EXTI7_IRQ_PRI,
+		__stm32_exti_isr_7, DEVICE_GET(exti_stm32),
+		0);
+	IRQ_CONNECT(EXTI8_IRQn,
+		CONFIG_EXTI_STM32_EXTI8_IRQ_PRI,
+		__stm32_exti_isr_8, DEVICE_GET(exti_stm32),
+		0);
+	IRQ_CONNECT(EXTI9_IRQn,
+		CONFIG_EXTI_STM32_EXTI9_IRQ_PRI,
+		__stm32_exti_isr_9, DEVICE_GET(exti_stm32),
+		0);
+	IRQ_CONNECT(EXTI10_IRQn,
+		CONFIG_EXTI_STM32_EXTI10_IRQ_PRI,
+		__stm32_exti_isr_10, DEVICE_GET(exti_stm32),
+		0);
+	IRQ_CONNECT(EXTI11_IRQn,
+		CONFIG_EXTI_STM32_EXTI11_IRQ_PRI,
+		__stm32_exti_isr_11, DEVICE_GET(exti_stm32),
+		0);
+	IRQ_CONNECT(EXTI12_IRQn,
+		CONFIG_EXTI_STM32_EXTI12_IRQ_PRI,
+		__stm32_exti_isr_12, DEVICE_GET(exti_stm32),
+		0);
+	IRQ_CONNECT(EXTI13_IRQn,
+		CONFIG_EXTI_STM32_EXTI13_IRQ_PRI,
+		__stm32_exti_isr_13, DEVICE_GET(exti_stm32),
+		0);
+	IRQ_CONNECT(EXTI14_IRQn,
+		CONFIG_EXTI_STM32_EXTI14_IRQ_PRI,
+		__stm32_exti_isr_14, DEVICE_GET(exti_stm32),
+		0);
+	IRQ_CONNECT(EXTI15_IRQn,
+		CONFIG_EXTI_STM32_EXTI15_IRQ_PRI,
+		__stm32_exti_isr_15, DEVICE_GET(exti_stm32),
+		0);
+#endif /* CONFIG_SOC_SERIES_STM32MP1X */
+
 #if defined(CONFIG_SOC_SERIES_STM32F2X) || \
       defined(CONFIG_SOC_SERIES_STM32F4X) || \
       defined(CONFIG_SOC_SERIES_STM32F7X)

soc/arm/st_stm32/stm32mp1/soc.h

@@ -27,6 +27,10 @@
  */
 #include <kernel_includes.h>
 
+#ifdef CONFIG_EXTI_STM32
+#include <stm32mp1xx_ll_exti.h>
+#endif
+
 #endif /* !_ASMLANGUAGE */
 
 #endif /* _STM32MP1SOC_H_ */