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arch/x86: refactor arch.h

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Some of the elements of arch.h can be shared between subarches,
so put them in a common file and factor out the rest. Placeholder
left for the Intel64 definitions to be added later.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
This commit is contained in:
Charles E. Youse 2019-07-04 11:27:20 -07:00 • committed by Andrew Boie
commit 773cdf1c55
4 changed files with 87 additions and 68 deletions
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4
include/arch/cpu.h
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@ -9,8 +9,8 @@
#ifndef ZEPHYR_INCLUDE_ARCH_CPU_H_ #ifndef ZEPHYR_INCLUDE_ARCH_CPU_H_
#define ZEPHYR_INCLUDE_ARCH_CPU_H_ #define ZEPHYR_INCLUDE_ARCH_CPU_H_
#if defined(CONFIG_X86) && !defined(CONFIG_X86_LONGMODE) #if defined(CONFIG_X86)
#include <arch/x86/ia32/arch.h> #include <arch/x86/arch.h>
#elif defined(CONFIG_X86_64) #elif defined(CONFIG_X86_64)
#include <arch/x86_64/arch.h> #include <arch/x86_64/arch.h>
#elif defined(CONFIG_ARM) #elif defined(CONFIG_ARM)

76
include/arch/x86/arch.h Normal file
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@ -0,0 +1,76 @@
/*
* Copyright (c) 2019 Intel Corp.
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_X86_ARCH_H_
#define ZEPHYR_INCLUDE_ARCH_X86_ARCH_H_
#include <generated_dts_board.h>
#include <stdbool.h>
#include <irq.h>
#ifdef CONFIG_X86_LONGMODE
#include <arch/x86/intel64/arch.h>
#else
#include <arch/x86/ia32/arch.h>
#endif
#include <arch/common/ffs.h>
#ifndef _ASMLANGUAGE
extern void z_arch_irq_enable(unsigned int irq);
extern void z_arch_irq_disable(unsigned int irq);
extern u32_t z_timer_cycle_get_32(void);
#define z_arch_k_cycle_get_32() z_timer_cycle_get_32()
/**
* Returns true if interrupts were unlocked prior to the
* z_arch_irq_lock() call that produced the key argument.
*/
static ALWAYS_INLINE bool z_arch_irq_unlocked(unsigned int key)
{
return (key & 0x200) != 0;
}
/**
* @brief read timestamp register ensuring serialization
*/
static inline u64_t z_tsc_read(void)
{
union {
struct {
u32_t lo;
u32_t hi;
};
u64_t value;
} rv;
/* rdtsc & cpuid clobbers eax, ebx, ecx and edx registers */
__asm__ volatile (/* serialize */
"xorl %%eax,%%eax;\n\t"
"cpuid;\n\t"
:
:
: "%eax", "%ebx", "%ecx", "%edx"
);
/*
* We cannot use "=A", since this would use %rax on x86_64 and
* return only the lower 32bits of the TSC
*/
__asm__ volatile ("rdtsc" : "=a" (rv.lo), "=d" (rv.hi));
return rv.value;
}
static ALWAYS_INLINE void arch_nop(void)
{
__asm__ volatile("nop");
}
#endif /* _ASMLANGUAGE */
#endif /* ZEPHYR_INCLUDE_ARCH_X86_ARCH_H_ */

66
include/arch/x86/ia32/arch.h
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@ -14,11 +14,9 @@
#ifndef ZEPHYR_INCLUDE_ARCH_X86_IA32_ARCH_H_ #ifndef ZEPHYR_INCLUDE_ARCH_X86_IA32_ARCH_H_
#define ZEPHYR_INCLUDE_ARCH_X86_IA32_ARCH_H_ #define ZEPHYR_INCLUDE_ARCH_X86_IA32_ARCH_H_
#include <irq.h>
#include "sys_io.h" #include "sys_io.h"
#include <drivers/interrupt_controller/sysapic.h> #include <drivers/interrupt_controller/sysapic.h>
#include <kernel_arch_thread.h> #include <kernel_arch_thread.h>
#include <generated_dts_board.h>
#include <ia32/mmustructs.h> #include <ia32/mmustructs.h>
#include <stdbool.h> #include <stdbool.h>
#include <arch/common/ffs.h> #include <arch/common/ffs.h>
@ -369,38 +367,6 @@ static ALWAYS_INLINE void z_do_irq_unlock(void)
} }
/**
* @brief read timestamp register ensuring serialization
*/
static inline u64_t z_tsc_read(void)
{
union {
struct {
u32_t lo;
u32_t hi;
};
u64_t value;
} rv;
/* rdtsc & cpuid clobbers eax, ebx, ecx and edx registers */
__asm__ volatile (/* serialize */
"xorl %%eax,%%eax;\n\t"
"cpuid;\n\t"
:
:
: "%eax", "%ebx", "%ecx", "%edx"
);
/*
* We cannot use "=A", since this would use %rax on x86_64 and
* return only the lower 32bits of the TSC
*/
__asm__ volatile ("rdtsc" : "=a" (rv.lo), "=d" (rv.hi));
return rv.value;
}
/** /**
* *
* @brief Get a 32 bit CPU timestamp counter * @brief Get a 32 bit CPU timestamp counter
@ -481,24 +447,6 @@ static ALWAYS_INLINE void z_arch_irq_unlock(unsigned int key)
z_do_irq_unlock(); z_do_irq_unlock();
} }
/**
* Returns true if interrupts were unlocked prior to the
* z_arch_irq_lock() call that produced the key argument.
*/
static ALWAYS_INLINE bool z_arch_irq_unlocked(unsigned int key)
{
return (key & 0x200) != 0;
}
/**
* @brief Explicitly nop operation.
*/
static ALWAYS_INLINE void arch_nop(void)
{
__asm__ volatile("nop");
}
/** /**
* The NANO_SOFT_IRQ macro must be used as the value for the @a irq parameter * The NANO_SOFT_IRQ macro must be used as the value for the @a irq parameter
* to NANO_CPU_INT_REGISTER when connecting to an interrupt that does not * to NANO_CPU_INT_REGISTER when connecting to an interrupt that does not
@ -506,17 +454,6 @@ static ALWAYS_INLINE void arch_nop(void)
*/ */
#define NANO_SOFT_IRQ ((unsigned int) (-1)) #define NANO_SOFT_IRQ ((unsigned int) (-1))
/**
* @brief Enable a specific IRQ
* @param irq IRQ
*/
extern void z_arch_irq_enable(unsigned int irq);
/**
* @brief Disable a specific IRQ
* @param irq IRQ
*/
extern void z_arch_irq_disable(unsigned int irq);
/** /**
* @defgroup float_apis Floating Point APIs * @defgroup float_apis Floating Point APIs
* @ingroup kernel_apis * @ingroup kernel_apis
@ -562,9 +499,6 @@ extern void k_float_enable(struct k_thread *thread, unsigned int options);
extern void k_cpu_idle(void); extern void k_cpu_idle(void);
extern u32_t z_timer_cycle_get_32(void);
#define z_arch_k_cycle_get_32() z_timer_cycle_get_32()
#ifdef CONFIG_X86_ENABLE_TSS #ifdef CONFIG_X86_ENABLE_TSS
extern struct task_state_segment _main_tss; extern struct task_state_segment _main_tss;
#endif #endif

9
include/arch/x86/intel64/arch.h Normal file
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@ -0,0 +1,9 @@
/*
* Copyright (c) 2019 Intel Corp.
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_ARCH_X86_INTEL64_ARCH_H_
#define ZEPHYR_INCLUDE_ARCH_X86_INTEL64_ARCH_H_
#endif /* ZEPHYR_INCLUDE_ARCH_X86_INTEL64_ARCH_H_ */