i2c: dw: re-organize transfer related code
() Re-organize the steps involved in data transfer, according to the datasheet's flowchart. () Extract the common code for transfer initialization and put it into its own function. () i2c_write() and i2c_polling_write() are now using the common data sending function. Change-Id: Ieb90253ee10ddceb3b5d05b258e7fc6253d18729 Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Daniel Leung
Anas Nashif
parent
7551562a14
commit
76bfe7b3a1
2 changed files with 156 additions and 122 deletions
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@ -74,32 +74,62 @@ static inline void i2c_dw_memory_write(uint32_t base_addr, uint32_t offset,
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}
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static inline void _i2c_dw_data_ask(struct device *dev, uint8_t restart)
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{
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struct i2c_dw_rom_config const * const rom = dev->config->config_info;
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struct i2c_dw_dev_config * const dw = dev->driver_data;
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volatile struct i2c_dw_registers * const regs =
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(struct i2c_dw_registers *)rom->base_address;
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uint32_t data;
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/* No more bytes to request */
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if (dw->request_bytes == 0) {
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return;
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}
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/* Tell controller to get another byte */
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data = IC_DATA_CMD_CMD;
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/* Send restart if needed) */
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if (restart) {
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data |= IC_DATA_CMD_RESTART;
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}
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/* After receiving the last byte, send STOP */
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if (dw->request_bytes == 1) {
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data |= IC_DATA_CMD_STOP;
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}
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regs->ic_data_cmd.raw = data;
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dw->request_bytes--;
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}
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static void _i2c_dw_data_read(struct device *dev)
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{
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struct i2c_dw_rom_config const * const rom = dev->config->config_info;
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struct i2c_dw_dev_config * const dw = dev->driver_data;
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volatile struct i2c_dw_registers * const regs =
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(struct i2c_dw_registers *)rom->base_address;
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uint32_t i = 0;
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uint32_t rx_cnt = 0;
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/* Make sure we have some buffer to read/write to */
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while (regs->ic_status.bits.rfne && (dw->rx_len > 0)) {
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dw->rx_buffer[0] = regs->ic_data_cmd.raw;
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dw->rx_buffer += 1;
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dw->rx_len -= 1;
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if (dw->rx_len == 0) {
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break;
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}
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_i2c_dw_data_ask(dev, 0);
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}
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/* Nothing to receive anymore */
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if (dw->rx_len == 0) {
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dw->state &= ~I2C_DW_CMD_RECV;
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return;
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}
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rx_cnt = regs->ic_rxflr;
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if (rx_cnt > dw->rx_len) {
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rx_cnt = dw->rx_len;
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}
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for (i = 0; i < rx_cnt; i++) {
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dw->rx_buffer[i] = regs->ic_data_cmd.raw;
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}
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dw->rx_buffer += i;
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dw->rx_len -= i;
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}
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@ -109,55 +139,44 @@ static void _i2c_dw_data_send(struct device *dev)
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struct i2c_dw_dev_config * const dw = dev->driver_data;
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volatile struct i2c_dw_registers * const regs =
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(struct i2c_dw_registers *)rom->base_address;
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uint32_t i = 0;
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uint32_t tx_cnt = 0;
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uint32_t data = 0;
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/* Nothing to send anymore, mask the interrupt */
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if (dw->tx_len == 0) {
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regs->ic_intr_mask.bits.tx_empty = 0;
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if (dw->rx_len > 0) {
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/* Tell controller to grab a byte.
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* RESTART if something has ben sent.
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*/
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_i2c_dw_data_ask(dev, (dw->state & I2C_DW_CMD_SEND));
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/* QUIRK:
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* If requesting more than one byte, the process has
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* to be jump-started by requesting two bytes first.
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*/
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_i2c_dw_data_ask(dev, 0);
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}
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dw->state &= ~I2C_DW_CMD_SEND;
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if (dw->rx_tx_len == 0) {
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return;
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}
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tx_cnt = I2C_DW_FIFO_DEPTH - regs->ic_txflr;
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if (tx_cnt > dw->rx_tx_len) {
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tx_cnt = dw->rx_tx_len;
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}
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for (i = 0; i < tx_cnt; i++) {
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if (dw->tx_len > 0) {
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while (regs->ic_status.bits.tfnf && (dw->tx_len > 0)) {
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/* We have something to transmit to a specific host */
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data = dw->tx_buffer[i];
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data = dw->tx_buffer[0];
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/* Is this the last byte to write */
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if (dw->tx_len == 1) {
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data |= (dw->rx_len > 0) ?
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IC_DATA_CMD_RESTART : IC_DATA_CMD_STOP;
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}
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dw->tx_len -= 1;
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} else {
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/*
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* We want to send out a request to read data from a
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* specific host
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/* If this is the last byte to write
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* and nothing to receive, send STOP.
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*/
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data = IC_DATA_CMD_CMD;
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/* This is the last dummy byte to write */
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if (dw->rx_tx_len == 1) {
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if ((dw->tx_len == 1) && (dw->rx_len == 0)) {
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data |= IC_DATA_CMD_STOP;
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}
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}
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regs->ic_data_cmd.raw = data;
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dw->rx_tx_len -= 1;
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}
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dw->tx_buffer += i;
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if (dw->rx_tx_len <= 0) {
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regs->ic_intr_mask.bits.tx_empty = 0;
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regs->ic_intr_mask.bits.stop_det = 1;
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dw->tx_len -= 1;
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dw->tx_buffer += 1;
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}
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}
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@ -187,6 +206,8 @@ static inline void _i2c_dw_transfer_complete(struct device *dev)
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dw->cb(dev, cb_type);
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}
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}
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dw->state &= ~I2C_DW_BUSY;
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}
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void i2c_dw_isr(struct device *port)
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@ -209,7 +230,7 @@ void i2c_dw_isr(struct device *port)
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#endif
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/*
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* Causes of an intterrupt:
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* Causes of an interrupt:
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* - STOP condition is detected
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* - Transfer is aborted
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* - Transmit FIFO is empy
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@ -228,7 +249,7 @@ void i2c_dw_isr(struct device *port)
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* handled.
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*/
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if (regs->ic_intr_stat.bits.stop_det) {
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_i2c_dw_data_read(port);
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value = regs->ic_clr_stop_det;
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_i2c_dw_transfer_complete(port);
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}
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@ -239,7 +260,7 @@ void i2c_dw_isr(struct device *port)
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_i2c_dw_data_send(port);
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}
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/* Check if the Master RX buffer is full */
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/* Check if the RX FIFO reached threshold */
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if (regs->ic_intr_stat.bits.rx_full) {
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_i2c_dw_data_read(port);
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}
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@ -352,23 +373,31 @@ static int _i2c_dw_setup(struct device *dev)
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DBG("I2C: lcnt = %d\n", dw->lcnt);
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DBG("I2C: hcnt = %d\n", dw->hcnt);
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/* Set TX interrupt mode */
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ic_con.bits.tx_empty_ctl = 1;
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/* Set the IC_CON register */
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regs->ic_con = ic_con;
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/* END of setup IC_CON */
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/* Set RX fifo threshold level */
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regs->ic_rx_tl = (regs->ic_comp_param_1.bits.rx_buffer_depth / 2);
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/* Set TX fifo threshold level */
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regs->ic_tx_tl = (regs->ic_comp_param_1.bits.tx_buffer_depth / 2);
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/* Set RX fifo threshold level.
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* Setting it to zero automatically triggers interrupt
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* RX_FULL whenever there is data received.
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*
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* TODO: extend the threshold for multi-byte RX.
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*/
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regs->ic_rx_tl = 0;
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/* Set TX fifo threshold level.
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* TX_EMPTY interrupt is triggered only when the
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* TX FIFO is truly empty.
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*
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* TODO: threshold set to just enough for TX
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*/
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regs->ic_tx_tl = 0;
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return rc;
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}
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static int _i2c_dw_transfer(struct device *dev,
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static int _i2c_dw_transfer_init(struct device *dev,
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uint8_t *write_buf, uint32_t write_len,
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uint8_t *read_buf, uint32_t read_len,
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uint16_t slave_address)
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@ -378,22 +407,29 @@ static int _i2c_dw_transfer(struct device *dev,
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volatile struct i2c_dw_registers * const regs =
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(struct i2c_dw_registers *)rom->base_address;
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uint32_t value = 0;
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int ret;
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/* First step, check if there is current activity */
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if (regs->ic_status.bits.activity) {
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return DEV_FAIL;
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dw->state |= I2C_DW_BUSY;
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if (write_len > 0) {
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dw->state |= I2C_DW_CMD_SEND;
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}
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if (read_len > 0) {
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dw->state |= I2C_DW_CMD_RECV;
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}
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dw->rx_len = read_len;
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dw->rx_buffer = read_buf;
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dw->tx_len = write_len;
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dw->tx_buffer = write_buf;
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dw->rx_tx_len = dw->rx_len + dw->tx_len;
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dw->request_bytes = read_len;
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/* Disable the device controller to be able set TAR */
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regs->ic_enable.bits.enable = 0;
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_i2c_dw_setup(dev);
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ret = _i2c_dw_setup(dev);
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if (ret) {
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return ret;
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}
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/* Disable interrupts */
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regs->ic_intr_mask.raw = 0;
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@ -404,12 +440,43 @@ static int _i2c_dw_transfer(struct device *dev,
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if (regs->ic_con.bits.master_mode) {
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/* Set address of target slave */
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regs->ic_tar.bits.ic_tar = slave_address;
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} else {
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/* Set slave address for device */
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regs->ic_sar.bits.ic_sar = slave_address;
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}
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return DEV_OK;
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}
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static int _i2c_dw_transfer_start(struct device *dev,
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uint8_t *write_buf, uint32_t write_len,
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uint8_t *read_buf, uint32_t read_len,
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uint16_t slave_address)
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{
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struct i2c_dw_rom_config const * const rom = dev->config->config_info;
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volatile struct i2c_dw_registers * const regs =
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(struct i2c_dw_registers *)rom->base_address;
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int ret;
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/* First step, check if there is current activity */
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if (regs->ic_status.bits.activity) {
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return DEV_FAIL;
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}
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ret = _i2c_dw_transfer_init(dev, write_buf, write_len,
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read_buf, read_len, slave_address);
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if (ret) {
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return ret;
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}
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/* Trigger IRQ when TX_EMPTY */
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regs->ic_con.bits.tx_empty_ctl = 1;
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if (regs->ic_con.bits.master_mode) {
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/* Enable necessary interrupts */
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regs->ic_intr_mask.raw = (DW_ENABLE_TX_INT_I2C_MASTER |
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DW_ENABLE_RX_INT_I2C_MASTER);
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} else {
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/* Set slave address for device */
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regs->ic_sar.bits.ic_sar = slave_address;
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/* Enable necessary interrupts */
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regs->ic_intr_mask.raw = DW_ENABLE_TX_INT_I2C_SLAVE;
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}
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@ -430,8 +497,6 @@ static int i2c_dw_polling_write(struct device *dev,
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volatile struct i2c_dw_registers * const regs =
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(struct i2c_dw_registers *)rom->base_address;
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uint32_t value = 0;
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uint32_t i;
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uint32_t data;
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uint32_t start_time;
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int ret = DEV_OK;
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@ -448,43 +513,17 @@ static int i2c_dw_polling_write(struct device *dev,
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}
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}
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dw->rx_len = 0;
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dw->rx_buffer = NULL;
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dw->tx_len = write_len;
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dw->tx_buffer = write_buf;
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dw->rx_tx_len = dw->rx_len + dw->tx_len;
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/* Disable the device controller to be able set TAR */
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regs->ic_enable.bits.enable = 0;
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ret = _i2c_dw_setup(dev);
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ret = _i2c_dw_transfer_init(dev, write_buf, write_len,
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NULL, 0, slave_address);
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if (ret) {
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return ret;
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}
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/* Disable interrupts */
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regs->ic_intr_mask.raw = 0;
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/* Clear interrupts */
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value = regs->ic_clr_intr;
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/* Set address of target slave */
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regs->ic_tar.bits.ic_tar = slave_address;
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/* Enable controller */
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regs->ic_enable.bits.enable = 1;
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/* Transmit */
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i = 0;
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while (dw->tx_len > 0) {
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/* We have something to transmit to a specific host */
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data = dw->tx_buffer[i];
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/* Is this the last byte to write */
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if (dw->tx_len == 1) {
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data |= IC_DATA_CMD_STOP;
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}
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/* Wait for space in TX FIFO */
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start_time = nano_tick_get_32();
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while (!regs->ic_status.bits.tfnf) {
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@ -494,13 +533,15 @@ static int i2c_dw_polling_write(struct device *dev,
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}
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}
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regs->ic_data_cmd.raw = data;
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i += 1;
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dw->tx_len -= 1;
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dw->rx_tx_len -= 1;
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_i2c_dw_data_send(dev);
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}
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/* Finalize TX when there is nothing more to send as
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* the data send function has code to deal with the end of
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* TX phase.
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*/
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_i2c_dw_data_send(dev);
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/* Wait for transfer to complete */
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start_time = nano_tick_get_32();
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while (!regs->ic_raw_intr_stat.bits.stop_det) {
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@ -644,22 +685,14 @@ static int i2c_dw_set_callback(struct device *dev, i2c_callback cb)
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static int i2c_dw_write(struct device *dev, uint8_t *buf,
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uint32_t len, uint16_t slave_addr)
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{
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struct i2c_dw_dev_config * const dw = dev->driver_data;
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dw->state = I2C_DW_CMD_SEND;
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return _i2c_dw_transfer(dev, buf, len, 0, 0, slave_addr);
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return _i2c_dw_transfer_start(dev, buf, len, 0, 0, slave_addr);
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}
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static int i2c_dw_read(struct device *dev, uint8_t *buf,
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uint32_t len, uint16_t slave_addr)
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{
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struct i2c_dw_dev_config * const dw = dev->driver_data;
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dw->state = I2C_DW_CMD_RECV;
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return _i2c_dw_transfer(dev, 0, 0, buf, len, slave_addr);
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return _i2c_dw_transfer_start(dev, 0, 0, buf, len, slave_addr);
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}
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@ -55,6 +55,7 @@ typedef void (*i2c_isr_cb_t)(struct device *port);
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#define I2C_DW_CMD_SEND (1 << 0)
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#define I2C_DW_CMD_RECV (1 << 1)
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#define I2C_DW_CMD_ERROR (1 << 2)
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#define I2C_DW_BUSY (1 << 3)
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#define DW_ENABLE_TX_INT_I2C_MASTER (DW_INTR_STAT_TX_OVER | \
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@ -123,11 +124,11 @@ struct i2c_dw_dev_config {
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volatile uint8_t state; /* last direction of transfer */
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uint8_t slave_mode;
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uint8_t request_bytes;
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uint8_t rx_len;
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uint8_t *rx_buffer;
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uint8_t tx_len;
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uint8_t *tx_buffer;
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uint8_t rx_tx_len;
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bool support_hs_mode;
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uint16_t hcnt;
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