From 75f681b0d9bb6ad5a314b757d0a421158b476fa1 Mon Sep 17 00:00:00 2001 From: Ioannis Glaropoulos Date: Tue, 14 May 2019 09:00:10 +0200 Subject: [PATCH] soc: arm: add ARM MPU node info and fixup for Cortex-M7 SoCs Unlike Cortex-M3 and Cortex-M4, in Cortex-M7 the number of MPU regions may vary based on the implementation. This commit adds a DTS node for the ARM MPU peripheral in the device tree of Cortex-M7 SoCs and updates the fixup files, so we may extract the number of MPU regions at build time. SoCs: - nxp_rt - same70 - stm32f7 Signed-off-by: Ioannis Glaropoulos --- dts/arm/atmel/same70.dtsi | 8 ++++++++ dts/arm/nxp/nxp_rt.dtsi | 8 ++++++++ dts/arm/st/f7/stm32f7.dtsi | 8 ++++++++ soc/arm/atmel_sam/same70/dts_fixup.h | 2 ++ soc/arm/nxp_imx/rt/dts_fixup.h | 2 ++ soc/arm/st_stm32/stm32f7/dts_fixup.h | 2 ++ 6 files changed, 30 insertions(+) diff --git a/dts/arm/atmel/same70.dtsi b/dts/arm/atmel/same70.dtsi index 97fb24bbeb8..5fe700a5fcb 100644 --- a/dts/arm/atmel/same70.dtsi +++ b/dts/arm/atmel/same70.dtsi @@ -18,6 +18,14 @@ device_type = "cpu"; compatible = "arm,cortex-m7"; reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + mpu: mpu@e000ed90 { + compatible = "arm,armv7m-mpu"; + reg = <0xe000ed90 0x40>; + arm,num-mpu-regions = <16>; + }; }; }; diff --git a/dts/arm/nxp/nxp_rt.dtsi b/dts/arm/nxp/nxp_rt.dtsi index 01d67eeffc5..fd1e9528411 100644 --- a/dts/arm/nxp/nxp_rt.dtsi +++ b/dts/arm/nxp/nxp_rt.dtsi @@ -18,6 +18,14 @@ device_type = "cpu"; compatible = "arm,cortex-m7"; reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + mpu: mpu@e000ed90 { + compatible = "arm,armv7m-mpu"; + reg = <0xe000ed90 0x40>; + arm,num-mpu-regions = <16>; + }; }; }; diff --git a/dts/arm/st/f7/stm32f7.dtsi b/dts/arm/st/f7/stm32f7.dtsi index e53cbb52f1e..4af82d0c229 100644 --- a/dts/arm/st/f7/stm32f7.dtsi +++ b/dts/arm/st/f7/stm32f7.dtsi @@ -19,6 +19,14 @@ device_type = "cpu"; compatible = "arm,cortex-m7"; reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + mpu: mpu@e000ed90 { + compatible = "arm,armv7m-mpu"; + reg = <0xe000ed90 0x40>; + arm,num-mpu-regions = <8>; + }; }; }; diff --git a/soc/arm/atmel_sam/same70/dts_fixup.h b/soc/arm/atmel_sam/same70/dts_fixup.h index 453197e8b07..e5138c9519c 100644 --- a/soc/arm/atmel_sam/same70/dts_fixup.h +++ b/soc/arm/atmel_sam/same70/dts_fixup.h @@ -10,6 +10,8 @@ #define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_NUM_MPU_REGIONS DT_ARM_ARMV7M_MPU_E000ED90_ARM_NUM_MPU_REGIONS + #define DT_GPIO_SAM_PORTA_LABEL DT_ATMEL_SAM_GPIO_400E0E00_LABEL #define DT_GPIO_SAM_PORTA_BASE_ADDRESS DT_ATMEL_SAM_GPIO_400E0E00_BASE_ADDRESS #define DT_GPIO_SAM_PORTA_IRQ DT_ATMEL_SAM_GPIO_400E0E00_IRQ_0 diff --git a/soc/arm/nxp_imx/rt/dts_fixup.h b/soc/arm/nxp_imx/rt/dts_fixup.h index 855e8ded0af..9b0b5ef26ac 100644 --- a/soc/arm/nxp_imx/rt/dts_fixup.h +++ b/soc/arm/nxp_imx/rt/dts_fixup.h @@ -8,6 +8,8 @@ #define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_NUM_MPU_REGIONS DT_ARM_ARMV7M_MPU_E000ED90_ARM_NUM_MPU_REGIONS + #define DT_MCUX_CCM_BASE_ADDRESS DT_NXP_IMX_CCM_400FC000_BASE_ADDRESS #define DT_MCUX_CCM_NAME DT_NXP_IMX_CCM_400FC000_LABEL diff --git a/soc/arm/st_stm32/stm32f7/dts_fixup.h b/soc/arm/st_stm32/stm32f7/dts_fixup.h index 5b423b736da..57c33505f0a 100644 --- a/soc/arm/st_stm32/stm32f7/dts_fixup.h +++ b/soc/arm/st_stm32/stm32f7/dts_fixup.h @@ -4,6 +4,8 @@ #define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_NUM_MPU_REGIONS DT_ARM_ARMV7M_MPU_E000ED90_ARM_NUM_MPU_REGIONS + #define DT_GPIO_STM32_GPIOA_BASE_ADDRESS DT_ST_STM32_GPIO_40020000_BASE_ADDRESS #define DT_GPIO_STM32_GPIOA_CLOCK_BITS_0 DT_ST_STM32_GPIO_40020000_CLOCK_BITS_0 #define DT_GPIO_STM32_GPIOA_CLOCK_BUS_0 DT_ST_STM32_GPIO_40020000_CLOCK_BUS_0