drivers: spi_dw: add WORD only access support
In some hardware, e.g. ARC HS Development kit,the peripheral space of DesignWare SPI only allowes WORD access, byte acess will raise bus error. This commit adds support for this case Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
This commit is contained in:
parent
9eb379f2bf
commit
75a65a0ad1
3 changed files with 29 additions and 4 deletions
|
@ -35,6 +35,15 @@ config SPI_DW_FIFO_DEPTH
|
|||
SSI_RX_FIFO_DEPTH of the DesignWare Synchronous
|
||||
Serial Interface. Depth ranges from 2-256.
|
||||
|
||||
config SPI_DW_ACCESS_WORD_ONLY
|
||||
bool "DesignWare SPI only allows word access"
|
||||
default n
|
||||
depends on SPI_DW
|
||||
help
|
||||
In some case, e.g. ARC HS Development kit, the peripheral space of
|
||||
DesignWare SPI only allows word access, byte access will raise
|
||||
exception.
|
||||
|
||||
if SPI_0
|
||||
|
||||
config SPI_DW_PORT_0_INTERRUPT_SINGLE_LINE
|
||||
|
|
|
@ -206,12 +206,21 @@ struct spi_dw_data {
|
|||
#define z_extra_clock_off(...)
|
||||
|
||||
/* Based on those macros above, here are common helpers for some registers */
|
||||
DEFINE_MM_REG_WRITE(baudr, DW_SPI_REG_BAUDR, 16)
|
||||
|
||||
DEFINE_MM_REG_READ(txflr, DW_SPI_REG_TXFLR, 32)
|
||||
DEFINE_MM_REG_READ(rxflr, DW_SPI_REG_RXFLR, 32)
|
||||
|
||||
#ifdef CONFIG_SPI_DW_ACCESS_WORD_ONLY
|
||||
DEFINE_MM_REG_WRITE(baudr, DW_SPI_REG_BAUDR, 32)
|
||||
DEFINE_MM_REG_WRITE(imr, DW_SPI_REG_IMR, 32)
|
||||
DEFINE_MM_REG_READ(imr, DW_SPI_REG_IMR, 32)
|
||||
DEFINE_MM_REG_READ(isr, DW_SPI_REG_ISR, 32)
|
||||
#else
|
||||
DEFINE_MM_REG_WRITE(baudr, DW_SPI_REG_BAUDR, 16)
|
||||
DEFINE_MM_REG_WRITE(imr, DW_SPI_REG_IMR, 8)
|
||||
DEFINE_MM_REG_READ(imr, DW_SPI_REG_IMR, 8)
|
||||
DEFINE_MM_REG_READ(isr, DW_SPI_REG_ISR, 8)
|
||||
#endif
|
||||
|
||||
DEFINE_SET_BIT_OP(ssienr, DW_SPI_REG_SSIENR, DW_SPI_SSIENR_SSIEN_BIT)
|
||||
DEFINE_CLEAR_BIT_OP(ssienr, DW_SPI_REG_SSIENR, DW_SPI_SSIENR_SSIEN_BIT)
|
||||
|
|
|
@ -43,9 +43,6 @@ extern "C" {
|
|||
/* Register helpers */
|
||||
DEFINE_MM_REG_WRITE(ctrlr0, DW_SPI_REG_CTRLR0, 32)
|
||||
DEFINE_MM_REG_READ(ctrlr0, DW_SPI_REG_CTRLR0, 32)
|
||||
DEFINE_MM_REG_WRITE(ctrlr1, DW_SPI_REG_CTRLR1, 16)
|
||||
DEFINE_MM_REG_READ(ctrlr1, DW_SPI_REG_CTRLR1, 16)
|
||||
DEFINE_MM_REG_WRITE(ser, DW_SPI_REG_SER, 8)
|
||||
DEFINE_MM_REG_WRITE(txftlr, DW_SPI_REG_TXFTLR, 32)
|
||||
DEFINE_MM_REG_WRITE(rxftlr, DW_SPI_REG_RXFTLR, 32)
|
||||
DEFINE_MM_REG_READ(rxftlr, DW_SPI_REG_RXFTLR, 32)
|
||||
|
@ -54,6 +51,16 @@ DEFINE_MM_REG_WRITE(dr, DW_SPI_REG_DR, 32)
|
|||
DEFINE_MM_REG_READ(dr, DW_SPI_REG_DR, 32)
|
||||
DEFINE_MM_REG_READ(ssi_comp_version, DW_SPI_REG_SSI_COMP_VERSION, 32)
|
||||
|
||||
#ifdef CONFIG_SPI_DW_ACCESS_WORD_ONLY
|
||||
DEFINE_MM_REG_WRITE(ctrlr1, DW_SPI_REG_CTRLR1, 32)
|
||||
DEFINE_MM_REG_READ(ctrlr1, DW_SPI_REG_CTRLR1, 32)
|
||||
DEFINE_MM_REG_WRITE(ser, DW_SPI_REG_SER, 32)
|
||||
#else
|
||||
DEFINE_MM_REG_WRITE(ctrlr1, DW_SPI_REG_CTRLR1, 16)
|
||||
DEFINE_MM_REG_READ(ctrlr1, DW_SPI_REG_CTRLR1, 16)
|
||||
DEFINE_MM_REG_WRITE(ser, DW_SPI_REG_SER, 8)
|
||||
#endif
|
||||
|
||||
/* ICR is on a unique bit */
|
||||
DEFINE_TEST_BIT_OP(icr, DW_SPI_REG_ICR, DW_SPI_SR_ICR_BIT)
|
||||
#define clear_interrupts(addr) test_bit_icr(addr)
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue