From 7578035f4c6a55dd9683024353e35859bf1aa95b Mon Sep 17 00:00:00 2001
From: Savinay Dharmappa <savinay.dharmappa@intel.com>
Date: Sat, 1 Jul 2017 00:18:58 +0530
Subject: [PATCH] dts: x86: Add device tree support for quark_d2000
 microcontroller

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
---
 .../quark_d2000/Kconfig.defconfig.series      |  4 ++
 .../x86/soc/intel_quark/quark_d2000/linker.ld |  1 +
 dts/x86/Makefile                              |  1 +
 dts/x86/intel_quark_d2000.dtsi                | 57 +++++++++++++++++++
 dts/x86/mem.h                                 |  3 +
 5 files changed, 66 insertions(+)
 create mode 100644 dts/x86/intel_quark_d2000.dtsi

diff --git a/arch/x86/soc/intel_quark/quark_d2000/Kconfig.defconfig.series b/arch/x86/soc/intel_quark/quark_d2000/Kconfig.defconfig.series
index a8c7de72f34..1c5ace3c72f 100644
--- a/arch/x86/soc/intel_quark/quark_d2000/Kconfig.defconfig.series
+++ b/arch/x86/soc/intel_quark/quark_d2000/Kconfig.defconfig.series
@@ -19,9 +19,11 @@ config TOOLCHAIN_VARIANT
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 32000000
 
+if !HAS_DTS
 config PHYS_LOAD_ADDR
 	default 0x00180000 if XIP
 	default 0x00280000 if !XIP
+endif
 
 config RAM_SIZE
 	default 8
@@ -41,10 +43,12 @@ config LOAPIC_TIMER_IRQ
 config LOAPIC_TIMER_IRQ_PRIORITY
 	default 2
 
+if !HAS_DTS
 config PHYS_RAM_ADDR
 	default 0x00280000
 	help
 	This option specifies the physical SRAM address of this Soc.
+endif
 
 config QMSI
 	def_bool y
diff --git a/arch/x86/soc/intel_quark/quark_d2000/linker.ld b/arch/x86/soc/intel_quark/quark_d2000/linker.ld
index a0995b59005..53b6834e798 100644
--- a/arch/x86/soc/intel_quark/quark_d2000/linker.ld
+++ b/arch/x86/soc/intel_quark/quark_d2000/linker.ld
@@ -13,6 +13,7 @@
 
 #include <autoconf.h>
 
+#include <generated_dts_board.h>
 /* physical address of RAM (needed for correct __ram_phys_end symbol) */
 #define PHYS_RAM_ADDR    CONFIG_PHYS_RAM_ADDR
 
diff --git a/dts/x86/Makefile b/dts/x86/Makefile
index b5e071ad234..a8c24977834 100644
--- a/dts/x86/Makefile
+++ b/dts/x86/Makefile
@@ -1,4 +1,5 @@
 ifeq ($(CONFIG_HAS_DTS),y)
 dtb-$(CONFIG_SOC_QUARK_SE_C1000)	=	arduino_101.dts_compiled
+dtb-$(CONFIG_SOC_SERIES_QUARK_D2000)	=	quark_d2000_crb.dts_compiled
 always	:= $(dtb-y)
 endif
diff --git a/dts/x86/intel_quark_d2000.dtsi b/dts/x86/intel_quark_d2000.dtsi
new file mode 100644
index 00000000000..27e15fd7714
--- /dev/null
+++ b/dts/x86/intel_quark_d2000.dtsi
@@ -0,0 +1,57 @@
+#include "skeleton.dtsi"
+#include "mem.h"
+
+/ {
+	cpus {
+		cpu@0 {
+			compatible = "intel,quark";
+		};
+
+	};
+
+	flash0: flash@00180000 {
+		reg = <0x00180000 DT_FLASH_SIZE>;
+	};
+
+	sram0: memory@00280000 {
+		reg = <0x00280000 DT_SRAM_SIZE>;
+	};
+
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+
+		rtc: rtc@b0000400 {
+			compatible = "intel,qmsi-rtc";
+			reg = <0xb0000400 0x400>;
+			clock-frequency = <32768>;
+		};
+
+		uart0: uart@b0002000 {
+			compatible = "intel,qmsi-uart";
+			reg = <0xb0002000 0x400>;
+			label = "UART_0";
+
+			status = "disabled";
+		};
+
+		uart1: uart@b0002400 {
+			compatible = "intel,qmsi-uart";
+			reg = <0xb0002400 0x400>;
+			label = "UART_1";
+
+			status = "disabled";
+		};
+
+		gpio: gpio@b000c000 {
+			compatible = "intel,qmsi-gpio";
+			reg = <0xb00c00 0x400>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+	};
+};
diff --git a/dts/x86/mem.h b/dts/x86/mem.h
index 87272503c92..c803eba5357 100644
--- a/dts/x86/mem.h
+++ b/dts/x86/mem.h
@@ -6,6 +6,9 @@
 #if defined(CONFIG_SOC_QUARK_SE_C1000)
 #define DT_FLASH_SIZE		__SIZE_K(144)
 #define DT_SRAM_SIZE		__SIZE_K(55)
+#elif defined(CONFIG_SOC_QUARK_D2000)
+#define DT_FLASH_SIZE		__SIZE_K(32)
+#define DT_SRAM_SIZE		__SIZE_K(8)
 #else
 #error "Flash and RAM sizes not defined for this chip"
 #endif