michaelh/zephyr
1
0
Fork 0
Code Releases Activity

soc: npcx: add support for npcx9m7f

Browse source 
Add new SoC npcx9m7f support for npcx9 series.

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
This commit is contained in:
Jun Lin 2022-02-07 16:27:16 +08:00 • committed by Anas Nashif
commit 756babfa75
5 changed files with 63 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

40
dts/arm/nuvoton/npcx9m7f.dtsi Normal file
View file

@ -0,0 +1,40 @@
/*
* Copyright (c) 2022 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include "npcx9.dtsi"
/ {
flash0: flash@10070000 {
reg = <0x10070000 DT_SIZE_K(320)>;
};
flash1: flash@64000000 {
reg = <0x64000000 DT_SIZE_K(1024)>;
};
sram0: memory@200c0000 {
compatible = "mmio-sram";
reg = <0x200C0000 DT_SIZE_K(64)>;
};
soc-id {
device-id = <0x22>;
};
};
&spi_fiu0 {
int_flash: w25q80@0 {
compatible ="jedec,spi-nor";
/* 8388608 bits = 1 Mbytes */
size = <0x800000>;
label = "W25Q80";
reg = <0>;
spi-max-frequency = <50000000>;
status = "okay";
jedec-id = [ef 40 14];
};
};

1
soc/arm/nuvoton_npcx/Kconfig
View file

@ -41,6 +41,7 @@ config NPCX_HEADER_CHIP
default "npcx7m7" if SOC_NPCX7M7FC
default "npcx9m3" if SOC_NPCX9M3F
default "npcx9m6" if SOC_NPCX9M6F
default "npcx9m7" if SOC_NPCX9M7F
choice NPCX_HEADER_SPI_MAX_CLOCK_CHOICE
prompt "Clock rate to use for SPI flash"

7
soc/arm/nuvoton_npcx/common/ecst/ecst_args.py
View file

@ -45,11 +45,14 @@ FW_CRC_START_OFFSET_DEFAULT = 0x0
POINTER_OFFSET_DEFAULT = 0x0
# Chips: convert from name to index.
CHIPS_INFO = {'npcx7m5': {'ram_address': 0x100a8000, 'ram_size': 0x20000},
CHIPS_INFO = {
'npcx7m5': {'ram_address': 0x100a8000, 'ram_size': 0x20000},
'npcx7m6': {'ram_address': 0x10090000, 'ram_size': 0x40000},
'npcx7m7': {'ram_address': 0x10070000, 'ram_size': 0x60000},
'npcx9m3': {'ram_address': 0x10080000, 'ram_size': 0x50000},
'npcx9m6': {'ram_address': 0x10090000, 'ram_size': 0x40000}}
'npcx9m6': {'ram_address': 0x10090000, 'ram_size': 0x40000},
'npcx9m7': {'ram_address': 0x10070000, 'ram_size': 0x60000},
}
DEFAULT_CHIP = 'npcx7m6'
# RAM related values

11
soc/arm/nuvoton_npcx/npcx9/Kconfig.defconfig.npcx9m7f Normal file
View file

@ -0,0 +1,11 @@
# Nuvoton Cortex-M4 Embedded Controller
# Copyright (c) 2022 Nuvoton Technology Corporation.
# SPDX-License-Identifier: Apache-2.0
if SOC_NPCX9M7F
config SOC
default "npcx9m7f"
endif # SOC_NPCX9M7F

3
soc/arm/nuvoton_npcx/npcx9/Kconfig.soc
View file

@ -13,4 +13,7 @@ config SOC_NPCX9M3F
config SOC_NPCX9M6F
bool "NPCX9M6F"
config SOC_NPCX9M7F
bool "NPCX9M7F"
endchoice