soc: arm64: Add agilex5 soc folder and its configurations

Add Agilex5 soc folder, MMU table and its configurations for
Intel SoC FPGA Agilex5 platform for initial bring up.
Add ARM Cortex-a76 and Cortex-a55 HMP cluster type.

Signed-off-by: Teik Heng Chong <teik.heng.chong@intel.com>
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>

arch/arm64/core/Kconfig

@@ -57,6 +57,20 @@ config CPU_CORTEX_A72
 	help
 	  This option signifies the use of a Cortex-A72 CPU
 
+config CPU_CORTEX_A76
+	bool
+	select CPU_CORTEX_A
+	select ARMV8_A
+	help
+	  This option signifies the use of a Cortex-A76 CPU
+
+config CPU_CORTEX_A76_A55
+	bool
+	select CPU_CORTEX_A
+	select ARMV8_A
+	help
+	  This option signifies the use of a Cortex-A76 and A55 big little CPU cluster
+
 config CPU_CORTEX_R82
 	bool
 	select CPU_AARCH64_CORTEX_R

cmake/compiler/gcc/target_arm64.cmake

@@ -9,5 +9,10 @@ if(DEFINED GCC_M_ARCH)
   list(APPEND TOOLCHAIN_LD_FLAGS  -march=${GCC_M_ARCH})
 endif()
 
+if(DEFINED GCC_M_TUNE)
+  list(APPEND TOOLCHAIN_C_FLAGS   -mtune=${GCC_M_TUNE})
+  list(APPEND TOOLCHAIN_LD_FLAGS  -mtune=${GCC_M_TUNE})
+endif()
+
 list(APPEND TOOLCHAIN_C_FLAGS   -mabi=lp64)
 list(APPEND TOOLCHAIN_LD_FLAGS  -mabi=lp64)

cmake/gcc-m-cpu.cmake

@@ -75,6 +75,11 @@ elseif("${ARCH}" STREQUAL "arm64")
     set(GCC_M_CPU cortex-a53)
   elseif(CONFIG_CPU_CORTEX_A55)
     set(GCC_M_CPU cortex-a55)
+  elseif(CONFIG_CPU_CORTEX_A76)
+    set(GCC_M_CPU cortex-a76)
+  elseif(CONFIG_CPU_CORTEX_A76_A55)
+    set(GCC_M_CPU cortex-a76)
+    set(GCC_M_TUNE cortex-a76.cortex-a55)
   elseif(CONFIG_CPU_CORTEX_A72)
     set(GCC_M_CPU cortex-a72)
   elseif(CONFIG_CPU_CORTEX_R82)

soc/arm64/intel_socfpga/agilex5/CMakeLists.txt

@@ -0,0 +1,6 @@
+# Copyright (c) 2022 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+zephyr_library_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c)

soc/arm64/intel_socfpga/agilex5/Kconfig.defconfig.agilex5

@@ -0,0 +1,21 @@
+# Copyright (c) 2022 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_AGILEX5
+
+config SOC
+	default "intel_socfpga_agilex5"
+
+# must be >= the highest interrupt number used
+# - include the UART interrupts 173 or 204
+config NUM_IRQS
+	int
+	default 205
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	int
+	default 400000000
+
+config KERNEL_VM_SIZE
+	default 0x400000
+endif

soc/arm64/intel_socfpga/agilex5/Kconfig.defconfig.series

@@ -0,0 +1,11 @@
+# Copyright (c) 2022 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_AGILEX5
+
+config SOC_SERIES
+	default "agilex5"
+
+source "soc/arm64/intel_socfpga/agilex5/Kconfig.defconfig.agilex5*"
+
+endif # SOC_SERIES_AGILEX5

soc/arm64/intel_socfpga/agilex5/Kconfig.series

@@ -0,0 +1,10 @@
+# Copyright (c) 2022 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_AGILEX5
+	bool "Intel SoC FPGA Agilex5 Series"
+	select ARM64
+	select CPU_CORTEX_A76_A55
+	select SOC_FAMILY_INTEL_SOCFPGA
+	help
+		Enable support for Intel SoC FPGA Series

soc/arm64/intel_socfpga/agilex5/Kconfig.soc

@@ -0,0 +1,10 @@
+# Copyright (c) 2022 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+choice
+prompt "Intel SoC FPGA Agilex5"
+depends on SOC_SERIES_AGILEX5
+
+config SOC_AGILEX5
+	bool "Intel SoC FPGA Agilex5"
+endchoice

soc/arm64/intel_socfpga/agilex5/linker.ld

@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2022 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ */
+
+#include <zephyr/arch/arm64/scripts/linker.ld>

soc/arm64/intel_socfpga/agilex5/mmu_regions.c

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2022, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/arch/cpu.h>
+#include <zephyr/arch/arm64/arm_mmu.h>
+
+static const struct arm_mmu_region mmu_regions[] = {
+
+	/* System manager register that required by clock driver */
+	MMU_REGION_FLAT_ENTRY("SYSTEM_MANAGER",
+			      DT_REG_ADDR(DT_NODELABEL(sysmgr)),
+			      DT_REG_SIZE(DT_NODELABEL(sysmgr)),
+			      MT_DEVICE_nGnRnE | MT_P_RW_U_RW | MT_DEFAULT_SECURE_STATE),
+
+	MMU_REGION_FLAT_ENTRY("PINMUX",
+			      DT_REG_ADDR_BY_IDX(DT_NODELABEL(pinmux), 0),
+			      DT_REG_SIZE_BY_IDX(DT_NODELABEL(pinmux), 0),
+			      MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
+
+	MMU_REGION_FLAT_ENTRY("GIC_0",
+			      DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 0),
+			      DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 0),
+			      MT_DEVICE_nGnRnE | MT_P_RW_U_RW | MT_DEFAULT_SECURE_STATE),
+
+	MMU_REGION_FLAT_ENTRY("GIC_1",
+			      DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 1),
+			      DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 1),
+			      MT_DEVICE_nGnRnE | MT_P_RW_U_RW | MT_DEFAULT_SECURE_STATE),
+
+	MMU_REGION_FLAT_ENTRY("GIC_ITS",
+			      DT_REG_ADDR(DT_NODELABEL(its)),
+			      DT_REG_SIZE(DT_NODELABEL(its)),
+			      MT_DEVICE_nGnRnE | MT_P_RW_U_RW | MT_DEFAULT_SECURE_STATE),
+};
+
+const struct arm_mmu_config mmu_config = {
+	.num_regions = ARRAY_SIZE(mmu_regions),
+	.mmu_regions = mmu_regions,
+};

subsys/mgmt/mcumgr/grp/os_mgmt/include/os_mgmt_processor.h

@@ -95,6 +95,10 @@ extern "C" {
 #define PROCESSOR_NAME "cortex-a57"
 #elif defined(CONFIG_CPU_CORTEX_A72)
 #define PROCESSOR_NAME "cortex-a72"
+#elif defined(CONFIG_CPU_CORTEX_A76_A55)
+#define PROCESSOR_NAME "cortex-a76"
+#elif defined(CONFIG_CPU_CORTEX_A76)
+#define PROCESSOR_NAME "cortex-a76"
 #elif defined(CONFIG_CPU_CORTEX_R82)
 #define PROCESSOR_NAME "armv8.4-a+nolse"
 #endif