drivers: interrupt_controller: Add SweRV PIC support
Add support for the built-in Programmable Interrupt Controller found in the SweRV EH1 RISC-V CPU Signed-off-by: Olof Kindgren <olof.kindgren@gmail.com>
This commit is contained in:
Olof Kindgren
Anas Nashif
parent
cac5e8f251
commit
754d56891e
4 changed files with 270 additions and 0 deletions
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@ -13,3 +13,4 @@ zephyr_sources_ifdef(CONFIG_DW_ICTL dw_ictl.c)
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zephyr_sources_ifdef(CONFIG_RV32M1_INTMUX rv32m1_intmux.c)
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zephyr_sources_ifdef(CONFIG_SAM0_EIC sam0_eic.c)
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zephyr_sources_ifdef(CONFIG_VEXRISCV_LITEX_IRQ vexriscv_litex.c)
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zephyr_sources_ifdef(CONFIG_SWERV_PIC swerv_pic.c)
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@ -98,6 +98,12 @@ config PLIC
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Platform Level Interrupt Controller provides support
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for external interrupt lines defined by the RISC-V SoC;
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config SWERV_PIC
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bool "SweRV EH1 Programmable Interrupt Controller (PIC)"
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default n
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help
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Programmable Interrupt Controller for the SweRV EH1 RISC-V CPU;
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config VEXRISCV_LITEX_IRQ
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bool "VexRiscv LiteX Interrupt controller"
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depends on SOC_RISCV32_LITEX_VEXRISCV
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236
drivers/interrupt_controller/swerv_pic.c
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236
drivers/interrupt_controller/swerv_pic.c
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@ -0,0 +1,236 @@
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/*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @brief SweRV EH1 PIC driver
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*/
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#include <kernel.h>
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#include <arch/cpu.h>
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#include <init.h>
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#include <sw_isr_table.h>
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#define SWERV_PIC_MAX_NUM CONFIG_NUM_IRQS
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#define SWERV_PIC_MAX_ID (SWERV_PIC_MAX_NUM + RISCV_MAX_GENERIC_IRQ)
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#define SWERV_PIC_MAX_PRIO 16
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#define SWERV_PIC_mpiccfg 0x3000
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#define SWERV_PIC_meipl(s) (0x0 + (s)*4)
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#define SWERV_PIC_meip(x) (0x1000 + (x)*4)
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#define SWERV_PIC_meie(s) (0x2000 + (s)*4)
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#define SWERV_PIC_meigwctrl(s) (0x4000 + (s)*4)
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#define SWERV_PIC_meigwclr(s) (0x5000 + (s)*4)
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#define SWERV_PIC_meivt "0xBC8"
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#define SWERV_PIC_meipt "0xBC9"
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#define SWERV_PIC_meicpct "0xBCA"
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#define SWERV_PIC_meicidpl "0xBCB"
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#define SWERV_PIC_meicurpl "0xBCC"
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#define SWERV_PIC_meihap "0xFC8"
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#define swerv_piccsr(csr) SWERV_PIC_##csr
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#define swerv_pic_readcsr(csr, value) \
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volatile("csrr %0, "swerv_piccsr(csr) : "=r" (value))
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#define swerv_pic_writecsr(csr, value) \
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volatile("csrw "swerv_piccsr(csr)", %0" :: "rK" (value))
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static int save_irq;
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static u32_t swerv_pic_read(u32_t reg)
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{
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return *(volatile u32_t *)(DT_INST_0_SWERV_PIC_BASE_ADDRESS + reg);
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}
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static void swerv_pic_write(u32_t reg, u32_t val)
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{
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*(volatile u32_t *)(DT_INST_0_SWERV_PIC_BASE_ADDRESS + reg) = val;
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}
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void swerv_pic_irq_enable(u32_t irq)
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{
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u32_t key;
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if ((irq >= SWERV_PIC_MAX_ID) || (irq < RISCV_MAX_GENERIC_IRQ)) {
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return;
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}
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key = irq_lock();
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swerv_pic_write(SWERV_PIC_meie(irq - RISCV_MAX_GENERIC_IRQ), 1);
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irq_unlock(key);
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}
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void swerv_pic_irq_disable(u32_t irq)
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{
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u32_t key;
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if ((irq >= SWERV_PIC_MAX_ID) || (irq < RISCV_MAX_GENERIC_IRQ)) {
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return;
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}
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key = irq_lock();
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swerv_pic_write(SWERV_PIC_meie(irq - RISCV_MAX_GENERIC_IRQ), 0);
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irq_unlock(key);
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}
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int swerv_pic_irq_is_enabled(u32_t irq)
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{
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if ((irq >= SWERV_PIC_MAX_ID) || (irq < RISCV_MAX_GENERIC_IRQ)) {
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return -1;
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}
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return swerv_pic_read(SWERV_PIC_meie(irq - RISCV_MAX_GENERIC_IRQ))
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& 0x1;
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}
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void swerv_pic_set_priority(u32_t irq, u32_t priority)
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{
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u32_t key;
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if (irq <= RISCV_MAX_GENERIC_IRQ) {
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return;
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}
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if ((irq >= SWERV_PIC_MAX_ID) || (irq < RISCV_MAX_GENERIC_IRQ)) {
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return;
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}
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if (priority >= SWERV_PIC_MAX_PRIO) {
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return;
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}
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key = irq_lock();
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swerv_pic_write(SWERV_PIC_meipl(irq - RISCV_MAX_GENERIC_IRQ), priority);
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irq_unlock(key);
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}
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int swerv_pic_get_irq(void)
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{
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return save_irq;
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}
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static void swerv_pic_irq_handler(void *arg)
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{
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u32_t tmp;
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u32_t irq;
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struct _isr_table_entry *ite;
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/* trigger the capture of the interrupt source ID */
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__asm__ swerv_pic_writecsr(meicpct, 0);
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__asm__ swerv_pic_readcsr(meihap, tmp);
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irq = (tmp >> 2) & 0xff;
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save_irq = irq;
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if (irq == 0U || irq >= 64) {
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z_irq_spurious(NULL);
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}
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irq += RISCV_MAX_GENERIC_IRQ;
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/* Call the corresponding IRQ handler in _sw_isr_table */
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ite = (struct _isr_table_entry *)&_sw_isr_table[irq];
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if (ite->isr)
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ite->isr(ite->arg);
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swerv_pic_write(SWERV_PIC_meigwclr(irq), 0);
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}
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static int swerv_pic_init(struct device *dev)
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{
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ARG_UNUSED(dev);
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int i;
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/* Init priority order to 0, 0=lowest to 15=highest */
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swerv_pic_write(SWERV_PIC_mpiccfg, 0);
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/* Ensure that all interrupts are disabled initially */
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for (i = 1; i < SWERV_PIC_MAX_ID; i++) {
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swerv_pic_write(SWERV_PIC_meie(i), 0);
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}
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/* Set priority of each interrupt line to 0 initially */
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for (i = 1; i < SWERV_PIC_MAX_ID; i++) {
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swerv_pic_write(SWERV_PIC_meipl(i), 15);
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}
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/* Set property of each interrupt line to level-triggered/high */
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for (i = 1; i < SWERV_PIC_MAX_ID; i++) {
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swerv_pic_write(SWERV_PIC_meigwctrl(i), (0<<1)|(0<<0));
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}
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/* clear pending of each interrupt line */
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for (i = 1; i < SWERV_PIC_MAX_ID; i++) {
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swerv_pic_write(SWERV_PIC_meigwclr(i), 0);
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}
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/* No interrupts masked */
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__asm__ swerv_pic_writecsr(meipt, 0);
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__asm__ swerv_pic_writecsr(meicidpl, 0);
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__asm__ swerv_pic_writecsr(meicurpl, 0);
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/* Setup IRQ handler for SweRV PIC driver */
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IRQ_CONNECT(RISCV_MACHINE_EXT_IRQ,
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0,
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swerv_pic_irq_handler,
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NULL,
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0);
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/* Enable IRQ for SweRV PIC driver */
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irq_enable(RISCV_MACHINE_EXT_IRQ);
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return 0;
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}
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void arch_irq_enable(unsigned int irq)
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{
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u32_t mie;
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if (irq > RISCV_MAX_GENERIC_IRQ) {
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swerv_pic_irq_enable(irq);
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return;
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}
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/*
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* CSR mie register is updated using atomic instruction csrrs
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* (atomic read and set bits in CSR register)
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*/
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__asm__ volatile ("csrrs %0, mie, %1\n"
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: "=r" (mie)
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: "r" (1 << irq));
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}
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void arch_irq_disable(unsigned int irq)
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{
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u32_t mie;
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if (irq > RISCV_MAX_GENERIC_IRQ) {
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swerv_pic_irq_disable(irq);
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return;
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}
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/*
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* Use atomic instruction csrrc to disable device interrupt in mie CSR.
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* (atomic read and clear bits in CSR register)
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*/
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__asm__ volatile ("csrrc %0, mie, %1\n"
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: "=r" (mie)
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: "r" (1 << irq));
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};
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int arch_irq_is_enabled(unsigned int irq)
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{
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u32_t mie;
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if (irq > RISCV_MAX_GENERIC_IRQ)
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return swerv_pic_irq_is_enabled(irq);
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__asm__ volatile ("csrr %0, mie" : "=r" (mie));
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return !!(mie & (1 << irq));
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}
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SYS_INIT(swerv_pic_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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