soc: arm: Introduce Infineon CAT1/PSoC 6 SOC integration

Add initial version of Infineon CAT1/PSoC 6 SOC integration.

Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
This commit is contained in:
Nazar Palamar 2022-03-25 12:10:03 +02:00 committed by Carles Cufí
commit 750475f3b8
17 changed files with 602 additions and 0 deletions

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# Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or
# an affiliate of Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
zephyr_include_directories(common/)
add_subdirectory(${SOC_SERIES})

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# Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or
# an affiliate of Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
config SOC_FAMILY_INFINEON_CAT1
bool
config SOC_FAMILY_INFINEON_CAT1A
bool
if SOC_FAMILY_INFINEON_CAT1
source "soc/arm/infineon_cat1/*/Kconfig.soc"
config SOC_FAMILY
string
default "infineon_cat1"
endif # SOC_FAMILY_INFINEON_CAT1

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# Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or
# an affiliate of Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
source "soc/arm/infineon_cat1/*/Kconfig.defconfig"

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# Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or
# an affiliate of Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
source "soc/arm/infineon_cat1/*/Kconfig.series"

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# Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or
# an affiliate of Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
zephyr_sources(soc.c)
zephyr_include_directories(.)
# Add sections
zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1 NOINIT noinit.ld)
# Add section for cm0p image ROM
zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1A ROM_START SORT_KEY 0 rom_cm0image.ld)
# Add section for cm0p image RAM
zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1A RAM_SECTIONS SORT_KEY 0 ram_cm0image.ld)

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# Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or
# an affiliate of Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
if SOC_FAMILY_INFINEON_CAT1
source "soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc.*"
config SOC_SERIES
default "psoc6"
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 100000000
config SOC_PSOC6_CM0P_IMAGE_ROM_SIZE
hex
default 0x2000 if SOC_PSOC6_CM0P_IMAGE_SLEEP
config SOC_PSOC6_CM0P_IMAGE_RAM_SIZE
hex
default 0x2000 if SOC_PSOC6_CM0P_IMAGE_SLEEP
endif # SOC_FAMILY_INFINEON_CAT1A

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# Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or
# an affiliate of Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
source "soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc.*"

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# Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
# an affiliate of Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
# Infineon PSoC6_02 based MCU default configuration
if SOC_DIE_PSOC6_02
config NUM_IRQS
default 32 if CPU_CORTEX_M0PLUS
default 168 if CPU_CORTEX_M4
config SOC
default "CYB0644ABZI_S2D44" if SOC_CYB0644ABZI_S2D44
default "CYS0644ABZI_S2D44" if SOC_CYS0644ABZI_S2D44
default "CY8C624ABZI_S2D44A0" if SOC_CY8C624ABZI_S2D44A0
default "CY8C624ABZI_S2D44" if SOC_CY8C624ABZI_S2D44
default "CY8C624AAZI_S2D44" if SOC_CY8C624AAZI_S2D44
default "CY8C624AFNI_S2D43" if SOC_CY8C624AFNI_S2D43
default "CY8C624ABZI_S2D04" if SOC_CY8C624ABZI_S2D04
default "CY8C624ABZI_S2D14" if SOC_CY8C624ABZI_S2D14
default "CY8C624AAZI_S2D14" if SOC_CY8C624AAZI_S2D14
default "CY8C6248AZI_S2D14" if SOC_CY8C6248AZI_S2D14
default "CY8C6248BZI_S2D44" if SOC_CY8C6248BZI_S2D44
default "CY8C6248AZI_S2D44" if SOC_CY8C6248AZI_S2D44
default "CY8C6248FNI_S2D43" if SOC_CY8C6248FNI_S2D43
default "CY8C614ABZI_S2F04" if SOC_CY8C614ABZI_S2F04
default "CY8C614AAZI_S2F04" if SOC_CY8C614AAZI_S2F04
default "CY8C614AFNI_S2F03" if SOC_CY8C614AFNI_S2F03
default "CY8C614AAZI_S2F14" if SOC_CY8C614AAZI_S2F14
default "CY8C614ABZI_S2F44" if SOC_CY8C614ABZI_S2F44
default "CY8C614AAZI_S2F44" if SOC_CY8C614AAZI_S2F44
default "CY8C614AFNI_S2F43" if SOC_CY8C614AFNI_S2F43
default "CY8C6148BZI_S2F44" if SOC_CY8C6148BZI_S2F44
default "CY8C6148AZI_S2F44" if SOC_CY8C6148AZI_S2F44
default "CY8C6148FNI_S2F43" if SOC_CY8C6148FNI_S2F43
default "CY8C624ABZI_D44" if SOC_CY8C624ABZI_D44
default "CY8C624ALQI_S2D42" if SOC_CY8C624ALQI_S2D42
default "CY8C624ALQI_S2D02" if SOC_CY8C624ALQI_S2D02
default "CY8C6248LQI_S2D42" if SOC_CY8C6248LQI_S2D42
default "CY8C6248LQI_S2D02" if SOC_CY8C6248LQI_S2D02
default "CY8C614ALQI_S2F42" if SOC_CY8C614ALQI_S2F42
default "CY8C614ALQI_S2F02" if SOC_CY8C614ALQI_S2F02
default "CY8C6148LQI_S2F42" if SOC_CY8C6148LQI_S2F42
default "CY8C6148LQI_S2F02" if SOC_CY8C6148LQI_S2F02
# add additional die specific params
endif # SOC_DIE_PSOC6_02

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# Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or
# an affiliate of Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
# Cypress PSoC™ 6 MCU lines
config SOC_SERIES_PSOC_60
bool "Infineon PSoC™ 60 series MCU(Value Line)"
select SOC_FAMILY_INFINEON_CAT1
help
Enable support for Infineon PSoC™ 60 MCU series
config SOC_SERIES_PSOC_61
bool "Infineon PSoC™ 61 series MCU (Programmable Line)"
select SOC_FAMILY_INFINEON_CAT1
help
Enable support for Infineon PSoC™ 61 MCU series
config SOC_SERIES_PSOC_62
bool "Infineon PSoC™ 62 series MCU (Performance Line)"
select SOC_FAMILY_INFINEON_CAT1
help
Enable support for Infineon PSoC™ 62 MCU series
config SOC_SERIES_PSOC_63
bool "Infineon PSoC™ 63 series MCU (Connectivity Line)"
select SOC_FAMILY_INFINEON_CAT1
help
Enable support for Infineon PSoC™ 63 MCU series
config SOC_SERIES_PSOC_64
bool "Infineon PSoC™ 64 series MCU (Security Line)"
select SOC_FAMILY_INFINEON_CAT1
help
Enable support for Infineon PSoC™ 64 MCU series

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# Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or
# an affiliate of Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
# Infineon PSoC6 die
config SOC_DIE_PSOC6
bool
select ARM
select CPU_CORTEX_M4
select CPU_HAS_ARM_MPU
select SOC_FAMILY_INFINEON_CAT1A
select DYNAMIC_INTERRUPTS
# Infineon PSoC6_01 die
config SOC_DIE_PSOC6_01
bool
select SOC_DIE_PSOC6
# Infineon PSoC6_02 die
config SOC_DIE_PSOC6_02
bool
select SOC_DIE_PSOC6
# Infineon PSoC6_03 die
config SOC_DIE_PSOC6_03
bool
select SOC_DIE_PSOC6
# Infineon PSoC6_04 die
config SOC_DIE_PSOC6_04
bool
select SOC_DIE_PSOC6
# Infineon soc packages
config SOC_PACKAGE_PSOC6_01_124_BGA
bool
config SOC_PACKAGE_PSOC6_01_116_BGA_BLE
bool
config SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE
bool
config SOC_PACKAGE_PSOC6_01_80_WLCSP
bool
config SOC_PACKAGE_PSOC6_01_116_BGA_USB
bool
config SOC_PACKAGE_PSOC6_01_124_BGA_SIP
bool
config SOC_PACKAGE_PSOC6_01_43_SMT
bool
config SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE_USB
bool
config SOC_PACKAGE_PSOC6_01_68_QFN_BLE
bool
config SOC_PACKAGE_PSOC6_02_124_BGA
bool
config SOC_PACKAGE_PSOC6_02_128_TQFP
bool
config SOC_PACKAGE_PSOC6_02_100_WLCSP
bool
config SOC_PACKAGE_PSOC6_02_68_QFN
bool
config SOC_PACKAGE_PSOC6_03_100_TQFP
bool
config SOC_PACKAGE_PSOC6_03_68_QFN
bool
config SOC_PACKAGE_PSOC6_03_49_WLCSP
bool
config SOC_PACKAGE_PSOC6_04_64_TQFP
bool
config SOC_PACKAGE_PSOC6_04_68_QFN
bool
config SOC_PACKAGE_PSOC6_04_80_TQFP
bool
## Infineon MCUs
choice
prompt "MPN"
osource "soc/arm/infineon_cat1/psoc6/Kconfig.soc.psoc6_*"
endchoice
if SOC_FAMILY_INFINEON_CAT1A
## PSoC™ 6 Cortex M0+ prebuilt images
choice
prompt "PSoC™ 6 Cortex M0+ prebuilt images"
help
Choose the prebuilt application image to be executed on the Cortex-M0+ core of the PSoC™ 6
dual-core MCU. The image is responsible for booting the Cortex-M4 on the device.
config SOC_PSOC6_CM0P_IMAGE_SLEEP
bool "DeepSleep"
help
DeepSleep prebuilt application image is executed on the Cortex-M0+ core of the PSoC™ 6 BLE
dual-core MCU.The image is provided as C array ready to be compiled as part of the Cortex-M4
application. The Cortex-M0+ application code is placed to internal flash by the Cortex-M4
linker script.
endchoice
endif # SOC_FAMILY_INFINEON_CAT1A

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# Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
# an affiliate of Cypress Semiconductor Corporation
# SPDX-License-Identifier: Apache-2.0
# Infineon PSoC6_02 series MCUs
config SOC_CYB0644ABZI_S2D44
bool "CYB0644ABZI_S2D44"
select SOC_DIE_PSOC6_02
select SOC_PACKAGE_PSOC6_02_124_BGA
depends on SOC_SERIES_PSOC_64
config SOC_CYS0644ABZI_S2D44
bool "CYS0644ABZI_S2D44"
select SOC_DIE_PSOC6_02
select SOC_PACKAGE_PSOC6_02_124_BGA
depends on SOC_SERIES_PSOC_64
config SOC_CY8C624ABZI_S2D44A0
bool "CY8C624ABZI_S2D44A0"
select SOC_DIE_PSOC6_02
select SOC_PACKAGE_PSOC6_02_124_BGA
depends on SOC_SERIES_PSOC_62
config SOC_CY8C624ABZI_S2D44
bool "CY8C624ABZI_S2D44"
select SOC_DIE_PSOC6_02
select SOC_PACKAGE_PSOC6_02_124_BGA
depends on SOC_SERIES_PSOC_62
config SOC_CY8C624AAZI_S2D44
bool "CY8C624AAZI_S2D44"
select SOC_DIE_PSOC6_02
select SOC_PACKAGE_PSOC6_02_128_TQFP
depends on SOC_SERIES_PSOC_62
config SOC_CY8C624AFNI_S2D43
bool "CY8C624AFNI_S2D43"
select SOC_DIE_PSOC6_02
select SOC_PACKAGE_PSOC6_02_100_WLCSP
depends on SOC_SERIES_PSOC_62
config SOC_CY8C624ABZI_S2D04
bool "CY8C624ABZI_S2D04"
select SOC_DIE_PSOC6_02
select SOC_PACKAGE_PSOC6_02_124_BGA
depends on SOC_SERIES_PSOC_62
config SOC_CY8C624ABZI_S2D14
bool "CY8C624ABZI_S2D14"
select SOC_DIE_PSOC6_02
select SOC_PACKAGE_PSOC6_02_124_BGA
depends on SOC_SERIES_PSOC_62
config SOC_CY8C624AAZI_S2D14
bool "CY8C624AAZI_S2D14"
select SOC_DIE_PSOC6_02
select SOC_PACKAGE_PSOC6_02_128_TQFP
depends on SOC_SERIES_PSOC_62
config SOC_CY8C6248AZI_S2D14
bool "CY8C6248AZI_S2D14"
select SOC_DIE_PSOC6_02
select SOC_PACKAGE_PSOC6_02_128_TQFP
depends on SOC_SERIES_PSOC_62
config SOC_CY8C6248BZI_S2D44
bool "CY8C6248BZI_S2D44"
select SOC_DIE_PSOC6_02
select SOC_PACKAGE_PSOC6_02_124_BGA
depends on SOC_SERIES_PSOC_62
config SOC_CY8C6248AZI_S2D44
bool "CY8C6248AZI_S2D44"
select SOC_DIE_PSOC6_02
select SOC_PACKAGE_PSOC6_02_128_TQFP
depends on SOC_SERIES_PSOC_62
config SOC_CY8C6248FNI_S2D43
bool "CY8C6248FNI_S2D43"
select SOC_DIE_PSOC6_02
select SOC_PACKAGE_PSOC6_02_100_WLCSP
depends on SOC_SERIES_PSOC_62
config SOC_CY8C614ABZI_S2F04
bool "CY8C614ABZI_S2F04"
select SOC_DIE_PSOC6_02
select SOC_PACKAGE_PSOC6_02_124_BGA
depends on SOC_SERIES_PSOC_61
config SOC_CY8C614AAZI_S2F04
bool "CY8C614AAZI_S2F04"
select SOC_DIE_PSOC6_02
select SOC_PACKAGE_PSOC6_02_128_TQFP
depends on SOC_SERIES_PSOC_61
config SOC_CY8C614AFNI_S2F03
bool "CY8C614AFNI_S2F03"
select SOC_DIE_PSOC6_02
select SOC_PACKAGE_PSOC6_02_100_WLCSP
depends on SOC_SERIES_PSOC_61
config SOC_CY8C614AAZI_S2F14
bool "CY8C614AAZI_S2F14"
select SOC_DIE_PSOC6_02
select SOC_PACKAGE_PSOC6_02_128_TQFP
depends on SOC_SERIES_PSOC_61
config SOC_CY8C614ABZI_S2F44
bool "CY8C614ABZI_S2F44"
select SOC_DIE_PSOC6_02
select SOC_PACKAGE_PSOC6_02_124_BGA
depends on SOC_SERIES_PSOC_61
config SOC_CY8C614AAZI_S2F44
bool "CY8C614AAZI_S2F44"
select SOC_DIE_PSOC6_02
select SOC_PACKAGE_PSOC6_02_128_TQFP
depends on SOC_SERIES_PSOC_61
config SOC_CY8C614AFNI_S2F43
bool "CY8C614AFNI_S2F43"
select SOC_DIE_PSOC6_02
select SOC_PACKAGE_PSOC6_02_100_WLCSP
depends on SOC_SERIES_PSOC_61
config SOC_CY8C6148BZI_S2F44
bool "CY8C6148BZI_S2F44"
select SOC_DIE_PSOC6_02
select SOC_PACKAGE_PSOC6_02_124_BGA
depends on SOC_SERIES_PSOC_61
config SOC_CY8C6148AZI_S2F44
bool "CY8C6148AZI_S2F44"
select SOC_DIE_PSOC6_02
select SOC_PACKAGE_PSOC6_02_128_TQFP
depends on SOC_SERIES_PSOC_61
config SOC_CY8C6148FNI_S2F43
bool "CY8C6148FNI_S2F43"
select SOC_DIE_PSOC6_02
select SOC_PACKAGE_PSOC6_02_100_WLCSP
depends on SOC_SERIES_PSOC_61
config SOC_CY8C624ABZI_D44
bool "CY8C624ABZI_D44"
select SOC_DIE_PSOC6_02
select SOC_PACKAGE_PSOC6_02_124_BGA
depends on SOC_SERIES_PSOC_62
config SOC_CY8C624ALQI_S2D42
bool "CY8C624ALQI_S2D42"
select SOC_DIE_PSOC6_02
select SOC_PACKAGE_PSOC6_02_68_QFN
depends on SOC_SERIES_PSOC_62
config SOC_CY8C624ALQI_S2D02
bool "CY8C624ALQI_S2D02"
select SOC_DIE_PSOC6_02
select SOC_PACKAGE_PSOC6_02_68_QFN
depends on SOC_SERIES_PSOC_62
config SOC_CY8C6248LQI_S2D42
bool "CY8C6248LQI_S2D42"
select SOC_DIE_PSOC6_02
select SOC_PACKAGE_PSOC6_02_68_QFN
depends on SOC_SERIES_PSOC_62
config SOC_CY8C6248LQI_S2D02
bool "CY8C6248LQI_S2D02"
select SOC_DIE_PSOC6_02
select SOC_PACKAGE_PSOC6_02_68_QFN
depends on SOC_SERIES_PSOC_62
config SOC_CY8C614ALQI_S2F42
bool "CY8C614ALQI_S2F42"
select SOC_DIE_PSOC6_02
select SOC_PACKAGE_PSOC6_02_68_QFN
depends on SOC_SERIES_PSOC_61
config SOC_CY8C614ALQI_S2F02
bool "CY8C614ALQI_S2F02"
select SOC_DIE_PSOC6_02
select SOC_PACKAGE_PSOC6_02_68_QFN
depends on SOC_SERIES_PSOC_61
config SOC_CY8C6148LQI_S2F42
bool "CY8C6148LQI_S2F42"
select SOC_DIE_PSOC6_02
select SOC_PACKAGE_PSOC6_02_68_QFN
depends on SOC_SERIES_PSOC_61
config SOC_CY8C6148LQI_S2F02
bool "CY8C6148LQI_S2F02"
select SOC_DIE_PSOC6_02
select SOC_PACKAGE_PSOC6_02_68_QFN
depends on SOC_SERIES_PSOC_61

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/*
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/arch/arm/aarch32/cortex_m/scripts/linker.ld>

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/*
* Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
. = ALIGN(4);
KEEP(*(.cy_sharedmem))

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/*
* Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/* Cortex-M0+ application ram image area */
SECTION_PROLOGUE(.ram_m0p_image,(NOLOAD),)
{
. = CONFIG_SOC_PSOC6_CM0P_IMAGE_RAM_SIZE;
} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)

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/*
* Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/* Cortex-M0+ application flash image area */
. = ALIGN(4);
__cy_m0p_code_start = . ;
KEEP(*(.cy_m0p_image))
. = CONFIG_SOC_PSOC6_CM0P_IMAGE_ROM_SIZE;
__cy_m0p_code_end = . ;

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/*
* Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief Infineon PSoC 6 SOC.
*/
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <cy_sysint.h>
cy_en_sysint_status_t Cy_SysInt_Init(const cy_stc_sysint_t *config, cy_israddress userIsr)
{
CY_ASSERT_L3(CY_SYSINT_IS_PRIORITY_VALID(config->intrPriority));
cy_en_sysint_status_t status = CY_SYSINT_SUCCESS;
/* The interrupt vector will be relocated only if the vector table was
* moved to SRAM (CONFIG_DYNAMIC_INTERRUPTS and CONFIG_GEN_ISR_TABLES
* must be enabled). Otherwise it is ignored.
*/
#if (CY_CPU_CORTEX_M0P)
#error Cy_SysInt_Init does not support CM0p core.
#endif /* (CY_CPU_CORTEX_M0P) */
#if defined(CONFIG_DYNAMIC_INTERRUPTS) && defined(CONFIG_GEN_ISR_TABLES)
if (config != NULL) {
uint32_t priority;
/* NOTE:
* PendSV IRQ (which is used in Cortex-M variants to implement thread
* context-switching) is assigned the lowest IRQ priority level.
* If priority is same as PendSV, we will catch assertion in
* z_arm_irq_priority_set function. To avoid this, change priority
* to IRQ_PRIO_LOWEST, if it > IRQ_PRIO_LOWEST. Macro IRQ_PRIO_LOWEST
* takes in to account PendSV specific.
*/
priority = (config->intrPriority > IRQ_PRIO_LOWEST) ?
IRQ_PRIO_LOWEST : config->intrPriority;
/* Configure a dynamic interrupt */
(void) irq_connect_dynamic(config->intrSrc, priority,
(void *) userIsr, NULL, 0);
} else {
status = CY_SYSINT_BAD_PARAM;
}
#endif /* defined(CONFIG_DYNAMIC_INTERRUPTS) && defined(CONFIG_GEN_ISR_TABLES) */
return status;
}
static int init_cycfg_platform_wraper(const struct device *arg)
{
ARG_UNUSED(arg);
/* Initializes the system */
SystemInit();
return 0;
}
SYS_INIT(init_cycfg_platform_wraper, PRE_KERNEL_1, 0);

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/*
* Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief Infineon PSoC 6 SOC.
*/
#ifndef _SOC__H_
#define _SOC__H_
#ifndef _ASMLANGUAGE
#include <cy_device_headers.h>
#endif /* !_ASMLANGUAGE */
#endif /* _SOC__H_ */