From 74f07b04ff4f72a46b3b6064ecd61cb4a14b2297 Mon Sep 17 00:00:00 2001 From: Jun Lin Date: Fri, 10 Nov 2023 10:38:21 +0800 Subject: [PATCH] soc: npcx: shi: add new registers for npcx4 Add the SHI enhanced buffer mode register definition for npcx4. Signed-off-by: Jun Lin --- soc/arm/nuvoton_npcx/common/reg/reg_def.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/soc/arm/nuvoton_npcx/common/reg/reg_def.h b/soc/arm/nuvoton_npcx/common/reg/reg_def.h index e9ef3460e63..21c0d99a87f 100644 --- a/soc/arm/nuvoton_npcx/common/reg/reg_def.h +++ b/soc/arm/nuvoton_npcx/common/reg/reg_def.h @@ -1619,7 +1619,11 @@ struct shi_reg { volatile uint8_t EVSTAT2; /* 0x010: Event Enable 2 */ volatile uint8_t EVENABLE2; - volatile uint8_t reserved4[15]; + /* 0x011: SHI Configuration 6 - only in chips which support enhanced buffer mode */ + volatile uint8_t SHICFG6; + /* 0x012: Single Byte Output Buffer - only in chips which support enhanced buffer mode */ + volatile uint8_t SBOBUF; + volatile uint8_t reserved4[13]; /* 0x20~0x9F: Output Buffer */ volatile uint8_t OBUF[128]; /* 0xA0~0x11F: Input Buffer */ @@ -1670,5 +1674,7 @@ struct shi_reg { #define NPCX_EVENABLE2_IBHF2EN 0 #define NPCX_EVENABLE2_CSNREEN 1 #define NPCX_EVENABLE2_CSNFEEN 2 +#define NPCX_SHICFG6_EBUFMD 0 +#define NPCX_SHICFG6_OBUF_SL 1 #endif /* _NUVOTON_NPCX_REG_DEF_H */