Board: amd : add board support for the Audio DSP on ACP_6_0 soc.

Create a acp_6_0_adsp board support for
the Audio DSP on ACP soc.

Signed-off-by: DineshKumar Kalva <DineshKumar.Kalva@amd.com>

boards/amd/acp_6_0_adsp/Kconfig.acp_6_0_adsp

@@ -1,4 +1,5 @@
 # Copyright (c) 2024 AMD
 # SPDX-License-Identifier: Apache-2.0
 
-zephyr_include_directories(include)
+config BOARD_ACP_6_0_ADSP
+select SOC_ACP_6_0

boards/amd/acp_6_0_adsp/acp_6_0_acp_adsp.dts

@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2024 AMD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <amd/acp_6_0.dtsi>
+
+/ {
+	model = "AMD ACP_6_0  Audio DSP";
+	compatible = "acp_6_0";
+};

boards/amd/acp_6_0_adsp/acp_6_0_adsp.yml

@@ -0,0 +1,14 @@
+#
+# Copyright 2024 AMD
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: acp_6_0_adsp/acp_6_0
+name: AMD ACP6.0  Audio DSP
+type: mcu
+arch: xtensa
+toolchain:
+  - zephyr
+  - xcc
+vendor: amd

boards/amd/acp_6_0_adsp/acp_6_0_adsp_defconfig

@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_GEN_ISR_TABLES=y
+CONFIG_GEN_IRQ_VECTOR_TABLE=y
+CONFIG_XTENSA_RESET_VECTOR=y
+CONFIG_OUTPUT_SYMBOLS=y
+CONFIG_MULTI_LEVEL_INTERRUPTS=n
+CONFIG_2ND_LEVEL_INTERRUPTS=n
+CONFIG_DCACHE_LINE_SIZE_DETECT=n
+CONFIG_DCACHE_LINE_SIZE=128

boards/amd/acp_6_0_adsp/board.cmake

@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: Apache-2.0
+board_set_flasher_ifnset(misc-flasher)
+board_finalize_runner_args(misc-flasher)
+board_set_rimage_target(rmb)

boards/amd/acp_6_0_adsp/board.yml

@@ -0,0 +1,6 @@
+board:
+  name: acp_6_0_adsp
+  full_name: ACP 6.0 Xtensa Audio DSP
+  vendor: amd
+  socs:
+    - name: acp_6_0

boards/amd/acp_6_0_adsp/doc/index.rst

@@ -0,0 +1,109 @@
+.. zephyr:board:: acp_6_0_adsp
+
+Overview
+********
+
+ACP 6.0 is Audio co-processor in AMD SoC based on HiFi5 DSP Xtensa Architecture,
+Zephyr OS is ported to run various audio and speech use cases on
+the SOF based framework.
+
+SOF can be built with either Zephyr or Cadence's proprietary
+Xtensa OS (XTOS) and run on a ACP 6.0 AMD platforms.
+
+Hardware
+********
+
+- Board features:
+
+  - RAM: 1.75MB HP SRAM & 512KB configurable IRAM/DRAM
+  - Audio Interfaces:
+
+      - 1 x SP (I2S, PCM),
+      - 1 x BT (I2S, PCM),
+      - 1 x HS (I2S, PCM),
+      - DMIC
+
+Supported Features
+==================
+
+The following hardware features are supported:
+
++-----------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component                    |
++===========+============+=====================================+
+| I2S       | on-chip    | I2S controller                      |
++-----------+------------+-------------------------------------+
+| DMIC(PDM) | on-chip    | PDM controller                      |
++-----------+------------+-------------------------------------+
+
+System Clock
+============
+
+The ACP 6.0 SoC operates with an audio clock frequency ranging from 200 to 800 MHz.
+
+System requirements
+*******************
+
+Xtensa Toolchain (optional)
+===========================
+
+The Zephyr SDK provides GCC-based toolchains necessary to build Zephyr for
+the AMD ACP boards. For users looking for higher optimization levels,
+building with the proprietary Xtensa toolchain from Cadence
+might be preferable.
+
+The following instructions assume you have purchased and
+installed the toolchain(s) and core(s) for your board following
+instructions from Xtensa documentation.
+
+If you choose to build with the Xtensa toolchain instead of the Zephyr SDK, set
+the following environment variables specific to the board in addition to the
+Xtensa toolchain environment variable listed below.
+
+First, make sure, the necessary license is available from
+Cadence and set the license variables as per the instruction from Cadence.
+Next, set the following environment variables:
+
+The bottom three variables are specific to acp_6_0.
+
+.. code-block:: shell
+
+   export XTENSA_TOOLCHAIN_PATH="tools installed path"
+   export XTENSA_BUILDS_DIR="user build directory path"
+   export ZEPHYR_TOOLCHAIN_VARIANT=xcc
+   export TOOLCHAIN_VER=RI-2019.1-linux
+   export XTENSA_CORE=LX7_HiFi5_PROD
+
+Programming and Debugging
+*************************
+
+Building
+========
+
+Build as usual.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: acp_6_0_adsp/acp_6_0
+   :goals: build
+
+Flashing
+========
+
+AMD supports only signed images flashing on ACP 6.0 platforms
+through ACP Linux Driver.
+
+The following boot sequence messages can be observed in dmesg
+
+   -  booting DSP firmware
+   -  ACP_DSP0_RUNSTALL : 0x0
+   -  ipc rx: 0x70000000
+   -  Firmware info: version 2:11:99-03a9d
+   -  Firmware: ABI 3:29:1 Kernel ABI 3:23:0
+   -  mailbox upstream 0x0 - size 0x400
+   -  mailbox downstream 0x400 - size 0x400
+   -  stream region 0x1000 - size 0x400
+   -  debug region 0x800 - size 0x400
+   -  fw_state change: 3 -> 6
+   -  ipc rx done: 0x70000000
+   -  firmware boot complete

soc/amd/acp_6_0/CMakeLists.txt

@@ -1,6 +1,3 @@
-if(CONFIG_SOC_ACP_6_0)
-  zephyr_include_directories(adsp)
-  add_subdirectory(adsp)
 # See detailed comments in soc/xtensa/intel_adsp/common/CMakeLists.txt
 add_custom_target(zephyr.ri ALL
   DEPENDS ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri
@@ -12,4 +9,3 @@ add_custom_command(
   DEPENDS ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME}
 )
 set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/adsp/linker.ld CACHE INTERNAL "")
-endif()

soc/amd/acp_6_0/Kconfig

@@ -2,6 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 config SOC_ACP_6_0
 	select XTENSA
+	select XTENSA_GEN_HANDLERS
 	select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang")
 	select XTENSA_RESET_VECTOR
 	select ATOMIC_OPERATIONS_BUILTIN

soc/amd/acp_6_0/Kconfig.defconfig

@@ -3,26 +3,23 @@
 
 if SOC_ACP_6_0
 config DCACHE_LINE_SIZE
-default 128
+	default 128
 
 config CACHE_MANAGEMENT
-default n
+	default n
 
 config XTENSA_TIMER
-default y
+	default y
 
 config SYS_CLOCK_HW_CYCLES_PER_SEC
-default 600000000 if XTENSA_TIMER
+	default 600000000 if XTENSA_TIMER
-
-config KERNEL_ENTRY
-default "__start"
 
 config MULTI_LEVEL_INTERRUPTS
-default n
+	default n
 
 config 2ND_LEVEL_INTERRUPTS
-default n
+	default n
 
 config KERNEL_ENTRY
-default "__start"
+	default "__start"
 endif

soc/amd/acp_6_0/adsp/_soc_inthandlers.h

@@ -1,165 +0,0 @@
-/*
- * Copyright (c) 2024 AMD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-/*
- * THIS FILE WAS AUTOMATICALLY GENERATED.  DO NOT EDIT.
- *
- * Functions here are designed to produce efficient code to
- * search an Xtensa bitmask of interrupts, inspecting only those bits
- * declared to be associated with a given interrupt level.  Each
- * dispatcher will handle exactly one flagged interrupt, in numerical
- * order (low bits first) and will return a mask of that bit that can
- * then be cleared by the calling code.  Unrecognized bits for the
- * level will invoke an error handler.
- */
-
-#include <xtensa/config/core-isa.h>
-#include <zephyr/sys/util.h>
-#include <zephyr/sw_isr_table.h>
-
-#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 1
-#error core-isa.h interrupt level does not match dispatcher!
-#endif
-#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 1
-#error core-isa.h interrupt level does not match dispatcher!
-#endif
-#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 1
-#error core-isa.h interrupt level does not match dispatcher!
-#endif
-#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 1
-#error core-isa.h interrupt level does not match dispatcher!
-#endif
-#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 2
-#error core-isa.h interrupt level does not match dispatcher!
-#endif
-#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 3
-#error core-isa.h interrupt level does not match dispatcher!
-#endif
-#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 4
-#error core-isa.h interrupt level does not match dispatcher!
-#endif
-#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 5
-#error core-isa.h interrupt level does not match dispatcher!
-#endif
-#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 7
-#error core-isa.h interrupt level does not match dispatcher!
-#endif
-
-static inline int _xtensa_handle_one_int1(unsigned int mask)
-{
-	int irq;
-
-	if (mask & 0x3) {
-		if (mask & BIT(0)) {
-			mask = BIT(0);
-			irq = 0;
-			goto handle_irq;
-		}
-		if (mask & BIT(1)) {
-			mask = BIT(1);
-			irq = 1;
-			goto handle_irq;
-		}
-	} else {
-		if (mask & BIT(6)) {
-			mask = BIT(6);
-			irq = 6;
-			goto handle_irq;
-		}
-		if (mask & BIT(8)) {
-			mask = BIT(8);
-			irq = 8;
-			goto handle_irq;
-		}
-	}
-	return 0;
-handle_irq:
-	_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
-	return mask;
-}
-
-static inline int _xtensa_handle_one_int2(unsigned int mask)
-{
-	int irq;
-
-	if (mask & BIT(2)) {
-		mask = BIT(2);
-		irq = 2;
-		goto handle_irq;
-	}
-	return 0;
-handle_irq:
-	_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
-	return mask;
-}
-
-static inline int _xtensa_handle_one_int3(unsigned int mask)
-{
-	int irq;
-
-	if (mask & BIT(3)) {
-		mask = BIT(3);
-		irq = 3;
-		goto handle_irq;
-	}
-	return 0;
-handle_irq:
-	_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
-	return mask;
-}
-
-static inline int _xtensa_handle_one_int4(unsigned int mask)
-{
-	int irq;
-
-	if (mask & BIT(4)) {
-		mask = BIT(4);
-		irq = 4;
-		goto handle_irq;
-	}
-	return 0;
-handle_irq:
-	_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
-	return mask;
-}
-
-static inline int _xtensa_handle_one_int5(unsigned int mask)
-{
-	int irq;
-
-	if (mask & BIT(5)) {
-		mask = BIT(5);
-		irq = 5;
-		goto handle_irq;
-	}
-	return 0;
-handle_irq:
-	_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
-	return mask;
-}
-
-static inline int _xtensa_handle_one_int7(unsigned int mask)
-{
-	int irq;
-
-	if (mask & BIT(7)) {
-		mask = BIT(7);
-		irq = 7;
-		goto handle_irq;
-	}
-	return 0;
-handle_irq:
-	_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
-	return mask;
-}
-
-static inline int _xtensa_handle_one_int0(unsigned int mask)
-{
-	return 0;
-}
-static inline int _xtensa_handle_one_int6(unsigned int mask)
-{
-	return 0;
-}

soc/amd/acp_6_0/adsp/include/adsp/cache.h

@@ -1,10 +0,0 @@
-/*
- * Copyright (c) 2024 AMD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef __COMMON_ADSP_CACHE_H__
-#define __COMMON_ADSP_CACHE_H__
-#include <xtensa/hal.h>
-#endif

soc/amd/acp_6_0/adsp/include/adsp/io.h

@@ -1,40 +0,0 @@
-/*
- * Copyright (c) 2024 AMD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef __INCLUDE_IO__
-#define __INCLUDE_IO__
-
-#include <stdint.h>
-#include <soc/memory.h>
-#include <zephyr/sys/sys_io.h>
-#include <zephyr/arch/common/sys_io.h>
-
-static inline uint32_t io_reg_read(uint32_t reg)
-{
-	return sys_read32(reg);
-}
-
-static inline void io_reg_write(uint32_t reg, uint32_t val)
-{
-	sys_write32(val, reg);
-}
-
-static inline void io_reg_update_bits(uint32_t reg, uint32_t mask, uint32_t value)
-{
-	io_reg_write(reg, (io_reg_read(reg) & (~mask)) | (value & mask));
-}
-
-static inline uint16_t io_reg_read16(uint32_t reg)
-{
-	return sys_read16(reg);
-}
-
-static inline void io_reg_write16(uint32_t reg, uint16_t val)
-{
-	sys_write16(val, reg);
-}
-
-#endif