Board: amd : add board support for the Audio DSP on ACP_6_0 soc.
Create a acp_6_0_adsp board support for the Audio DSP on ACP soc. Signed-off-by: DineshKumar Kalva <DineshKumar.Kalva@amd.com>
This commit is contained in:
DineshKumar Kalva
Anas Nashif
parent
173cc387a0
commit
749192a9fb
13 changed files with 167 additions and 230 deletions
|
|
@ -1,6 +1,3 @@
|
|||
if(CONFIG_SOC_ACP_6_0)
|
||||
zephyr_include_directories(adsp)
|
||||
add_subdirectory(adsp)
|
||||
# See detailed comments in soc/xtensa/intel_adsp/common/CMakeLists.txt
|
||||
add_custom_target(zephyr.ri ALL
|
||||
DEPENDS ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri
|
||||
|
|
@ -12,4 +9,3 @@ add_custom_command(
|
|||
DEPENDS ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME}
|
||||
)
|
||||
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/adsp/linker.ld CACHE INTERNAL "")
|
||||
endif()
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
config SOC_ACP_6_0
|
||||
select XTENSA
|
||||
select XTENSA_GEN_HANDLERS
|
||||
select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang")
|
||||
select XTENSA_RESET_VECTOR
|
||||
select ATOMIC_OPERATIONS_BUILTIN
|
||||
|
|
|
|||
|
|
@ -3,26 +3,23 @@
|
|||
|
||||
if SOC_ACP_6_0
|
||||
config DCACHE_LINE_SIZE
|
||||
default 128
|
||||
default 128
|
||||
|
||||
config CACHE_MANAGEMENT
|
||||
default n
|
||||
default n
|
||||
|
||||
config XTENSA_TIMER
|
||||
default y
|
||||
default y
|
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
default 600000000 if XTENSA_TIMER
|
||||
|
||||
config KERNEL_ENTRY
|
||||
default "__start"
|
||||
default 600000000 if XTENSA_TIMER
|
||||
|
||||
config MULTI_LEVEL_INTERRUPTS
|
||||
default n
|
||||
default n
|
||||
|
||||
config 2ND_LEVEL_INTERRUPTS
|
||||
default n
|
||||
default n
|
||||
|
||||
config KERNEL_ENTRY
|
||||
default "__start"
|
||||
default "__start"
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -1,4 +0,0 @@
|
|||
# Copyright (c) 2024 AMD
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
zephyr_include_directories(include)
|
||||
|
|
@ -1,165 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2024 AMD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
/*
|
||||
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
|
||||
*
|
||||
* Functions here are designed to produce efficient code to
|
||||
* search an Xtensa bitmask of interrupts, inspecting only those bits
|
||||
* declared to be associated with a given interrupt level. Each
|
||||
* dispatcher will handle exactly one flagged interrupt, in numerical
|
||||
* order (low bits first) and will return a mask of that bit that can
|
||||
* then be cleared by the calling code. Unrecognized bits for the
|
||||
* level will invoke an error handler.
|
||||
*/
|
||||
|
||||
#include <xtensa/config/core-isa.h>
|
||||
#include <zephyr/sys/util.h>
|
||||
#include <zephyr/sw_isr_table.h>
|
||||
|
||||
#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 1
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 2
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 3
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 4
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 5
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 7
|
||||
#error core-isa.h interrupt level does not match dispatcher!
|
||||
#endif
|
||||
|
||||
static inline int _xtensa_handle_one_int1(unsigned int mask)
|
||||
{
|
||||
int irq;
|
||||
|
||||
if (mask & 0x3) {
|
||||
if (mask & BIT(0)) {
|
||||
mask = BIT(0);
|
||||
irq = 0;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(1)) {
|
||||
mask = BIT(1);
|
||||
irq = 1;
|
||||
goto handle_irq;
|
||||
}
|
||||
} else {
|
||||
if (mask & BIT(6)) {
|
||||
mask = BIT(6);
|
||||
irq = 6;
|
||||
goto handle_irq;
|
||||
}
|
||||
if (mask & BIT(8)) {
|
||||
mask = BIT(8);
|
||||
irq = 8;
|
||||
goto handle_irq;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
handle_irq:
|
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
|
||||
return mask;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int2(unsigned int mask)
|
||||
{
|
||||
int irq;
|
||||
|
||||
if (mask & BIT(2)) {
|
||||
mask = BIT(2);
|
||||
irq = 2;
|
||||
goto handle_irq;
|
||||
}
|
||||
return 0;
|
||||
handle_irq:
|
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
|
||||
return mask;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int3(unsigned int mask)
|
||||
{
|
||||
int irq;
|
||||
|
||||
if (mask & BIT(3)) {
|
||||
mask = BIT(3);
|
||||
irq = 3;
|
||||
goto handle_irq;
|
||||
}
|
||||
return 0;
|
||||
handle_irq:
|
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
|
||||
return mask;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int4(unsigned int mask)
|
||||
{
|
||||
int irq;
|
||||
|
||||
if (mask & BIT(4)) {
|
||||
mask = BIT(4);
|
||||
irq = 4;
|
||||
goto handle_irq;
|
||||
}
|
||||
return 0;
|
||||
handle_irq:
|
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
|
||||
return mask;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int5(unsigned int mask)
|
||||
{
|
||||
int irq;
|
||||
|
||||
if (mask & BIT(5)) {
|
||||
mask = BIT(5);
|
||||
irq = 5;
|
||||
goto handle_irq;
|
||||
}
|
||||
return 0;
|
||||
handle_irq:
|
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
|
||||
return mask;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int7(unsigned int mask)
|
||||
{
|
||||
int irq;
|
||||
|
||||
if (mask & BIT(7)) {
|
||||
mask = BIT(7);
|
||||
irq = 7;
|
||||
goto handle_irq;
|
||||
}
|
||||
return 0;
|
||||
handle_irq:
|
||||
_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
|
||||
return mask;
|
||||
}
|
||||
|
||||
static inline int _xtensa_handle_one_int0(unsigned int mask)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline int _xtensa_handle_one_int6(unsigned int mask)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1,10 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2024 AMD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef __COMMON_ADSP_CACHE_H__
|
||||
#define __COMMON_ADSP_CACHE_H__
|
||||
#include <xtensa/hal.h>
|
||||
#endif
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2024 AMD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef __INCLUDE_IO__
|
||||
#define __INCLUDE_IO__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <soc/memory.h>
|
||||
#include <zephyr/sys/sys_io.h>
|
||||
#include <zephyr/arch/common/sys_io.h>
|
||||
|
||||
static inline uint32_t io_reg_read(uint32_t reg)
|
||||
{
|
||||
return sys_read32(reg);
|
||||
}
|
||||
|
||||
static inline void io_reg_write(uint32_t reg, uint32_t val)
|
||||
{
|
||||
sys_write32(val, reg);
|
||||
}
|
||||
|
||||
static inline void io_reg_update_bits(uint32_t reg, uint32_t mask, uint32_t value)
|
||||
{
|
||||
io_reg_write(reg, (io_reg_read(reg) & (~mask)) | (value & mask));
|
||||
}
|
||||
|
||||
static inline uint16_t io_reg_read16(uint32_t reg)
|
||||
{
|
||||
return sys_read16(reg);
|
||||
}
|
||||
|
||||
static inline void io_reg_write16(uint32_t reg, uint16_t val)
|
||||
{
|
||||
sys_write16(val, reg);
|
||||
}
|
||||
|
||||
#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue