From 743938b4502b8542ff3d87f399c6983713251076 Mon Sep 17 00:00:00 2001 From: Christian Taedcke Date: Wed, 17 Oct 2018 22:22:50 +0200 Subject: [PATCH] dts/arm/st_stm32: Add SPI nodes to STM32 F7 series This patch adds SPI nodes to STM32 F7 series, as well as the corresponding dts fixup entries. Signed-off-by: Christian Taedcke --- dts/arm/st/f7/stm32f7.dtsi | 66 ++++++++++++++++++++++++++++ soc/arm/st_stm32/stm32f7/dts_fixup.h | 30 +++++++++++++ 2 files changed, 96 insertions(+) diff --git a/dts/arm/st/f7/stm32f7.dtsi b/dts/arm/st/f7/stm32f7.dtsi index 49663c7db4e..2c1297e9e79 100644 --- a/dts/arm/st/f7/stm32f7.dtsi +++ b/dts/arm/st/f7/stm32f7.dtsi @@ -241,6 +241,72 @@ label = "I2C_3"; }; + spi1: spi@40013000 { + compatible = "st,stm32-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40013000 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>; + interrupts = <35 5>; + status = "disabled"; + label = "SPI_1"; + }; + + spi2: spi@40003800 { + compatible = "st,stm32-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40003800 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>; + interrupts = <36 5>; + status = "disabled"; + label = "SPI_2"; + }; + + spi3: spi@40003C00 { + compatible = "st,stm32-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40003C00 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>; + interrupts = <51 5>; + status = "disabled"; + label = "SPI_3"; + }; + + spi4: spi@40013400 { + compatible = "st,stm32-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40013400 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>; + interrupts = <84 5>; + status = "disabled"; + label = "SPI_4"; + }; + + spi5: spi@40015000 { + compatible = "st,stm32-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40015000 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>; + interrupts = <85 5>; + status = "disabled"; + label = "SPI_5"; + }; + + spi6: spi@40015400 { + compatible = "st,stm32-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40015400 0x400>; + clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00200000>; + interrupts = <86 5>; + status = "disabled"; + label = "SPI_6"; + }; + timers1: timers@40010000 { compatible = "st,stm32-timers"; reg = <0x40010000 0x400>; diff --git a/soc/arm/st_stm32/stm32f7/dts_fixup.h b/soc/arm/st_stm32/stm32f7/dts_fixup.h index 9ff2a9672fb..b80a5526745 100644 --- a/soc/arm/st_stm32/stm32f7/dts_fixup.h +++ b/soc/arm/st_stm32/stm32f7/dts_fixup.h @@ -74,6 +74,36 @@ #define CONFIG_I2C_3_ERROR_IRQ ST_STM32_I2C_V2_40005C00_IRQ_ERROR #define CONFIG_I2C_3_BITRATE ST_STM32_I2C_V2_40005C00_CLOCK_FREQUENCY +#define CONFIG_SPI_1_BASE_ADDRESS ST_STM32_SPI_40013000_BASE_ADDRESS +#define CONFIG_SPI_1_IRQ_PRI ST_STM32_SPI_40013000_IRQ_0_PRIORITY +#define CONFIG_SPI_1_NAME ST_STM32_SPI_40013000_LABEL +#define CONFIG_SPI_1_IRQ ST_STM32_SPI_40013000_IRQ_0 + +#define CONFIG_SPI_2_BASE_ADDRESS ST_STM32_SPI_40003800_BASE_ADDRESS +#define CONFIG_SPI_2_IRQ_PRI ST_STM32_SPI_40003800_IRQ_0_PRIORITY +#define CONFIG_SPI_2_NAME ST_STM32_SPI_40003800_LABEL +#define CONFIG_SPI_2_IRQ ST_STM32_SPI_40003800_IRQ_0 + +#define CONFIG_SPI_3_BASE_ADDRESS ST_STM32_SPI_40003C00_BASE_ADDRESS +#define CONFIG_SPI_3_IRQ_PRI ST_STM32_SPI_40003C00_IRQ_0_PRIORITY +#define CONFIG_SPI_3_NAME ST_STM32_SPI_40003C00_LABEL +#define CONFIG_SPI_3_IRQ ST_STM32_SPI_40003C00_IRQ_0 + +#define CONFIG_SPI_4_BASE_ADDRESS ST_STM32_SPI_40013400_BASE_ADDRESS +#define CONFIG_SPI_4_IRQ_PRI ST_STM32_SPI_40013400_IRQ_0_PRIORITY +#define CONFIG_SPI_4_NAME ST_STM32_SPI_40013400_LABEL +#define CONFIG_SPI_4_IRQ ST_STM32_SPI_40013400_IRQ_0 + +#define CONFIG_SPI_5_BASE_ADDRESS ST_STM32_SPI_40015000_BASE_ADDRESS +#define CONFIG_SPI_5_IRQ_PRI ST_STM32_SPI_40015000_IRQ_0_PRIORITY +#define CONFIG_SPI_5_NAME ST_STM32_SPI_40015000_LABEL +#define CONFIG_SPI_5_IRQ ST_STM32_SPI_40015000_IRQ_0 + +#define CONFIG_SPI_6_BASE_ADDRESS ST_STM32_SPI_40015400_BASE_ADDRESS +#define CONFIG_SPI_6_IRQ_PRI ST_STM32_SPI_40015400_IRQ_0_PRIORITY +#define CONFIG_SPI_6_NAME ST_STM32_SPI_40015400_LABEL +#define CONFIG_SPI_6_IRQ ST_STM32_SPI_40015400_IRQ_0 + #ifdef ST_STM32_OTGFS_50000000_BASE_ADDRESS #define CONFIG_USB_BASE_ADDRESS ST_STM32_OTGFS_50000000_BASE_ADDRESS #define CONFIG_USB_IRQ ST_STM32_OTGFS_50000000_IRQ_OTGFS