pinctrl: npcx: add DEV_CTLx configuration support
Add a new pinctrl type to control peripheral modules' specific IO characteristics such as tri-state, the power supply type selection (3.3V or 1.8V), and so on. In NPCX series, the corresponding registers/fields are irregular. This CL wraps these definitions to dt nodes and put them in pinctrl property if needed. Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
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6 changed files with 119 additions and 0 deletions
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@ -153,6 +153,16 @@ static void npcx_psl_input_detection_configure(const pinctrl_soc_pin_t *pin)
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}
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}
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}
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}
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static void npcx_device_control_configure(const pinctrl_soc_pin_t *pin)
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{
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const struct npcx_dev_ctl *ctrl = (const struct npcx_dev_ctl *)&pin->cfg.dev_ctl;
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const uintptr_t scfg_base = npcx_pinctrl_cfg.base_scfg;
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SET_FIELD(NPCX_DEV_CTL(scfg_base, ctrl->offest),
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FIELD(ctrl->field_offset, ctrl->field_size),
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ctrl->field_value);
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}
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/* Pinctrl API implementation */
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/* Pinctrl API implementation */
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
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uintptr_t reg)
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uintptr_t reg)
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@ -164,6 +174,9 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
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if (pins[i].flags.type == NPCX_PINCTRL_TYPE_PERIPH) {
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if (pins[i].flags.type == NPCX_PINCTRL_TYPE_PERIPH) {
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/* Configure peripheral device's pinmux functionality */
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/* Configure peripheral device's pinmux functionality */
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npcx_periph_configure(&pins[i], reg);
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npcx_periph_configure(&pins[i], reg);
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} else if (pins[i].flags.type == NPCX_PINCTRL_TYPE_DEVICE_CTRL) {
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/* Configure device's io characteristics */
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npcx_device_control_configure(&pins[i]);
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} else if (pins[i].flags.type == NPCX_PINCTRL_TYPE_PSL_IN) {
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} else if (pins[i].flags.type == NPCX_PINCTRL_TYPE_PSL_IN) {
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/* Configure SPL input's detection mode */
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/* Configure SPL input's detection mode */
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npcx_psl_input_detection_configure(&pins[i]);
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npcx_psl_input_detection_configure(&pins[i]);
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@ -5,7 +5,35 @@
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*/
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*/
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&pinctrl {
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&pinctrl {
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/* Prebuild nodes for peripheral device's characteristics (Optional) */
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/omit-if-no-ref/ vhif_lpc_sl: devctl-vhif-3p3v-lpc {
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dev-ctl = <0x0 2 2 0x01>;
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};
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/omit-if-no-ref/ vhif_espi_shi_sl: devctl-vhif-1p8v-espi-shi {
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dev-ctl = <0x0 2 2 0x02>;
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};
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/omit-if-no-ref/ ext_flash_tris_off: devctl-fiu-ext-tris-off {
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dev-ctl = <0x0 6 1 0x00>;
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};
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/omit-if-no-ref/ ext_flash_tris_on: devctl-fiu-ext-tris-on {
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dev-ctl = <0x0 6 1 0x01>;
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};
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/* Prebuild nodes for peripheral device's pin-muxing and pad properties */
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/* Prebuild nodes for peripheral device's pin-muxing and pad properties */
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/* Flash Interface Unit (FIU) */
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/omit-if-no-ref/ fiu_ext_io0_io1_clk_cs_gpa4_96_a2_a0: periph-fiu-ext {
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dev-ctl = <0x6 1 1 0x00>; /* Select to external flash */
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pinmux = <&alt0_gpio_no_fpip>;
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};
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/omit-if-no-ref/ int_flash_sl: periph-fiu-int {
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dev-ctl = <0x6 1 1 0x01>; /* Select to internal flash */
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/* No need for pin-muxing */
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};
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/* Host peripheral interfaces */
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/* Host peripheral interfaces */
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/omit-if-no-ref/ espi_lpc_gp46_47_51_52_53_54_55_57: periph-lpc-espi {
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/omit-if-no-ref/ espi_lpc_gp46_47_51_52_53_54_55_57: periph-lpc-espi {
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pinmux = <&alt1_no_lpc_espi>;
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pinmux = <&alt1_no_lpc_espi>;
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@ -5,7 +5,44 @@
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*/
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*/
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&pinctrl {
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&pinctrl {
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/* Prebuild nodes for peripheral device's characteristics (Optional) */
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/omit-if-no-ref/ vhif_lpc_sl: devctl-vhif-3p3v-lpc {
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dev-ctl = <0x0 2 2 0x01>;
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};
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/omit-if-no-ref/ vhif_espi_shi_sl: devctl-vhif-1p8v-espi-shi {
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dev-ctl = <0x0 2 2 0x02>;
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};
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/omit-if-no-ref/ ext_flash_tris_off: devctl-fiu-ext-tris-off {
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dev-ctl = <0x0 6 1 0x00>;
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};
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/omit-if-no-ref/ ext_flash_tris_on: devctl-fiu-ext-tris-on {
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dev-ctl = <0x0 6 1 0x01>;
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};
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/* Prebuild nodes for peripheral device's pin-muxing and pad properties */
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/* Prebuild nodes for peripheral device's pin-muxing and pad properties */
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/* Flash Interface Unit (FIU) */
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/omit-if-no-ref/ fiu_ext_io0_io1_clk_cs_gpa4_96_a2_a0: periph-fiu-ext {
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dev-ctl = <0x6 1 1 0x00>; /* Select to external flash */
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pinmux = <&alt0_gpio_no_fpip>;
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};
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/omit-if-no-ref/ ext_flash_cs1_gpa6: periph-ext-spi-flash-cs1 {
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pinmux = <&alt0_f_spi_cs1>;
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};
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/omit-if-no-ref/ int_flash_sl: periph-fiu-int {
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dev-ctl = <0x6 1 1 0x01>; /* Select to internal flash */
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/* No need for pin-muxing */
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};
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/omit-if-no-ref/ fiu_ext_quad_io2_io3_gp93_a7: periph-fiu-ext-quad {
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pinmux = <&alt0_f_spi_quad>;
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};
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/* Host peripheral interfaces */
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/* Host peripheral interfaces */
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/omit-if-no-ref/ espi_lpc_gp46_47_51_52_53_54_55_57: periph-lpc-espi {
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/omit-if-no-ref/ espi_lpc_gp46_47_51_52_53_54_55_57: periph-lpc-espi {
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pinmux = <&alt1_no_lpc_espi>;
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pinmux = <&alt1_no_lpc_espi>;
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@ -57,6 +57,9 @@ child-binding:
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pinmux:
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pinmux:
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type: phandle
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type: phandle
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description: Configurations of pinmux selection
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description: Configurations of pinmux selection
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dev-ctl:
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type: array
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description: Configurations of device control such as tri-state, io type and so on.
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periph-pupd:
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periph-pupd:
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type: array
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type: array
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description: |
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description: |
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@ -16,6 +16,7 @@
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*/
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*/
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enum npcx_pinctrl_type {
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enum npcx_pinctrl_type {
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NPCX_PINCTRL_TYPE_PERIPH,
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NPCX_PINCTRL_TYPE_PERIPH,
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NPCX_PINCTRL_TYPE_DEVICE_CTRL,
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NPCX_PINCTRL_TYPE_PSL_IN,
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NPCX_PINCTRL_TYPE_PSL_IN,
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NPCX_PINCTRL_TYPE_RESERVED,
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NPCX_PINCTRL_TYPE_RESERVED,
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};
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};
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@ -81,6 +82,23 @@ struct npcx_periph {
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uint16_t reserved: 2;
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uint16_t reserved: 2;
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} __packed;
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} __packed;
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/**
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* @brief NPCX device control structure
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*
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* Used to indicate the device's corresponding register/field for its io
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* characteristics such as tri-state, power supply type selection, and so on.
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*/
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struct npcx_dev_ctl {
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/** Related register offset for device configuration. */
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uint16_t offest: 5;
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/** Related register field offset for device control. */
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uint16_t field_offset: 3;
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/** Related register field size for device control. */
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uint16_t field_size: 3;
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/** field value */
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uint16_t field_value: 5;
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} __packed;
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/**
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/**
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* @brief NPCX Power Switch Logic (PSL) input pad configuration structure
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* @brief NPCX Power Switch Logic (PSL) input pad configuration structure
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*
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*
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@ -103,6 +121,7 @@ struct npcx_psl_input {
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struct npcx_pinctrl {
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struct npcx_pinctrl {
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union {
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union {
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struct npcx_periph periph;
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struct npcx_periph periph;
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struct npcx_dev_ctl dev_ctl;
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struct npcx_psl_input psl_in;
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struct npcx_psl_input psl_in;
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uint16_t cfg_word;
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uint16_t cfg_word;
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} cfg;
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} cfg;
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@ -163,6 +182,21 @@ typedef struct npcx_pinctrl pinctrl_soc_pin_t;
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.cfg.periph.inverted = DT_PHA(DT_PROP(node_id, prop), alts, inv), \
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.cfg.periph.inverted = DT_PHA(DT_PROP(node_id, prop), alts, inv), \
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},
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},
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/**
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* @brief Utility macro to initialize a periphral pinmux configuration.
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*
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* @param node_id Node identifier.
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* @param prop Property name for pinmux configuration. (i.e. 'pinmux')
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*/
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#define Z_PINCTRL_NPCX_DEVICE_CONTROL_INIT(node_id, prop) \
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{ \
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.flags.type = NPCX_PINCTRL_TYPE_DEVICE_CTRL, \
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.cfg.dev_ctl.offest = DT_PROP_BY_IDX(node_id, prop, 0), \
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.cfg.dev_ctl.field_offset = DT_PROP_BY_IDX(node_id, prop, 1), \
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.cfg.dev_ctl.field_size = DT_PROP_BY_IDX(node_id, prop, 2), \
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.cfg.dev_ctl.field_value = DT_PROP_BY_IDX(node_id, prop, 3), \
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},
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/**
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/**
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* @brief Utility macro to initialize a periphral pull-up/down configuration.
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* @brief Utility macro to initialize a periphral pull-up/down configuration.
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*
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*
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@ -227,6 +261,9 @@ typedef struct npcx_pinctrl pinctrl_soc_pin_t;
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COND_CODE_1(Z_PINCTRL_NPCX_HAS_PSL_IN_PROP(DT_PROP_BY_IDX(node_id, prop, idx)), \
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COND_CODE_1(Z_PINCTRL_NPCX_HAS_PSL_IN_PROP(DT_PROP_BY_IDX(node_id, prop, idx)), \
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(Z_PINCTRL_NPCX_PSL_IN_DETECT_CONF_INIT( \
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(Z_PINCTRL_NPCX_PSL_IN_DETECT_CONF_INIT( \
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DT_PROP_BY_IDX(node_id, prop, idx), psl_polarity)), ()) \
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DT_PROP_BY_IDX(node_id, prop, idx), psl_polarity)), ()) \
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COND_CODE_1(DT_NODE_HAS_PROP(DT_PROP_BY_IDX(node_id, prop, idx), dev_ctl), \
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(Z_PINCTRL_NPCX_DEVICE_CONTROL_INIT( \
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DT_PROP_BY_IDX(node_id, prop, idx), dev_ctl)), ()) \
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COND_CODE_1(DT_NODE_HAS_PROP(DT_PROP_BY_IDX(node_id, prop, idx), pinmux), \
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COND_CODE_1(DT_NODE_HAS_PROP(DT_PROP_BY_IDX(node_id, prop, idx), pinmux), \
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(Z_PINCTRL_NPCX_PERIPH_PINMUX_INIT( \
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(Z_PINCTRL_NPCX_PERIPH_PINMUX_INIT( \
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DT_PROP_BY_IDX(node_id, prop, idx), pinmux)), ())
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DT_PROP_BY_IDX(node_id, prop, idx), pinmux)), ())
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@ -254,6 +254,7 @@ static inline uint32_t npcx_lv_gpio_ctl_offset(uint32_t ctl_no)
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}
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}
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/* Macro functions for SCFG multi-registers */
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/* Macro functions for SCFG multi-registers */
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#define NPCX_DEV_CTL(base, n) (*(volatile uint8_t *)(base + n))
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#define NPCX_DEVALT(base, n) (*(volatile uint8_t *)(base + \
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#define NPCX_DEVALT(base, n) (*(volatile uint8_t *)(base + \
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npcx_devalt_offset(n)))
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npcx_devalt_offset(n)))
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#define NPCX_DEVALT_LK(base, n) (*(volatile uint8_t *)(base + \
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#define NPCX_DEVALT_LK(base, n) (*(volatile uint8_t *)(base + \
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