From 73c63f9ca6e07365c20d8bdce4597d2d5add3755 Mon Sep 17 00:00:00 2001 From: Hieu Nguyen Date: Wed, 14 May 2025 13:42:23 +0700 Subject: [PATCH] soc: renesas: Add initial support for Renesas RZ/V2N Add initial support for Renesas RZ/V2N Signed-off-by: Hieu Nguyen Signed-off-by: Tien Nguyen --- soc/renesas/rz/rzv2n/CMakeLists.txt | 8 ++++++++ soc/renesas/rz/rzv2n/Kconfig | 12 ++++++++++++ soc/renesas/rz/rzv2n/Kconfig.defconfig | 27 ++++++++++++++++++++++++++ soc/renesas/rz/rzv2n/Kconfig.soc | 24 +++++++++++++++++++++++ soc/renesas/rz/rzv2n/pinctrl_soc.h | 11 +++++++++++ soc/renesas/rz/rzv2n/soc.c | 21 ++++++++++++++++++++ soc/renesas/rz/rzv2n/soc.h | 12 ++++++++++++ soc/renesas/rz/soc.yml | 5 +++++ 8 files changed, 120 insertions(+) create mode 100644 soc/renesas/rz/rzv2n/CMakeLists.txt create mode 100644 soc/renesas/rz/rzv2n/Kconfig create mode 100644 soc/renesas/rz/rzv2n/Kconfig.defconfig create mode 100644 soc/renesas/rz/rzv2n/Kconfig.soc create mode 100644 soc/renesas/rz/rzv2n/pinctrl_soc.h create mode 100644 soc/renesas/rz/rzv2n/soc.c create mode 100644 soc/renesas/rz/rzv2n/soc.h diff --git a/soc/renesas/rz/rzv2n/CMakeLists.txt b/soc/renesas/rz/rzv2n/CMakeLists.txt new file mode 100644 index 00000000000..a58ca9b77f5 --- /dev/null +++ b/soc/renesas/rz/rzv2n/CMakeLists.txt @@ -0,0 +1,8 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(soc.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/rz/rzv2n/Kconfig b/soc/renesas/rz/rzv2n/Kconfig new file mode 100644 index 00000000000..1d935a7e51c --- /dev/null +++ b/soc/renesas/rz/rzv2n/Kconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RZV2N + select ARM + select CPU_CORTEX_M33 + select CPU_HAS_ARM_MPU + select HAS_RENESAS_RZ_FSP + select CPU_CORTEX_M_HAS_DWT + select SOC_EARLY_INIT_HOOK + select CPU_HAS_FPU + select ARMV8_M_DSP diff --git a/soc/renesas/rz/rzv2n/Kconfig.defconfig b/soc/renesas/rz/rzv2n/Kconfig.defconfig new file mode 100644 index 00000000000..c07b60c6296 --- /dev/null +++ b/soc/renesas/rz/rzv2n/Kconfig.defconfig @@ -0,0 +1,27 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RZV2N + +config NUM_IRQS + default 480 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +config FLASH_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + +config FLASH_BASE_ADDRESS + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +config SYS_CLOCK_EXISTS + default y + +config INIT_ARCH_HW_AT_BOOT + default y + +config BUILD_OUTPUT_S19 + default y + +endif # SOC_SERIES_RZV2N diff --git a/soc/renesas/rz/rzv2n/Kconfig.soc b/soc/renesas/rz/rzv2n/Kconfig.soc new file mode 100644 index 00000000000..d919cef9985 --- /dev/null +++ b/soc/renesas/rz/rzv2n/Kconfig.soc @@ -0,0 +1,24 @@ +# Copyright (c) 2025 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RZV2N + bool + select SOC_FAMILY_RENESAS_RZ + help + Renesas RZ/V2N series + +config SOC_SERIES + default "rzv2n" if SOC_SERIES_RZV2N + +config SOC_R9A09G056N48GBG + bool + select SOC_SERIES_RZV2N + help + R9A09G056N48GBG + +config SOC_R9A09G056N48GBG_CM33 + bool + select SOC_R9A09G056N48GBG + +config SOC + default "r9a09g056n48gbg" if SOC_R9A09G056N48GBG diff --git a/soc/renesas/rz/rzv2n/pinctrl_soc.h b/soc/renesas/rz/rzv2n/pinctrl_soc.h new file mode 100644 index 00000000000..d5c6def6ad8 --- /dev/null +++ b/soc/renesas/rz/rzv2n/pinctrl_soc.h @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_RENESAS_RZ_RZV2N_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_RENESAS_RZ_RZV2N_PINCTRL_SOC_H_ + +#include + +#endif /* ZEPHYR_SOC_RENESAS_RZ_RZV2N_PINCTRL_SOC_H_ */ diff --git a/soc/renesas/rz/rzv2n/soc.c b/soc/renesas/rz/rzv2n/soc.c new file mode 100644 index 00000000000..7f9081595e5 --- /dev/null +++ b/soc/renesas/rz/rzv2n/soc.c @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for Renesas RZ/V2N Group + */ + +#include +#include + +/* System core clock is set to 200 MHz after reset */ +uint32_t SystemCoreClock = 200000000; + +void soc_early_init_hook(void) +{ + bsp_clock_init(); +} diff --git a/soc/renesas/rz/rzv2n/soc.h b/soc/renesas/rz/rzv2n/soc.h new file mode 100644 index 00000000000..17c2b6b6717 --- /dev/null +++ b/soc/renesas/rz/rzv2n/soc.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2025 Renesas Electronics Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_RENESAS_RZV2N_SOC_H_ +#define ZEPHYR_SOC_RENESAS_RZV2N_SOC_H_ + +#include + +#endif /* ZEPHYR_SOC_RENESAS_RZV2N_SOC_H_ */ diff --git a/soc/renesas/rz/soc.yml b/soc/renesas/rz/soc.yml index dec9c482104..f720364e31e 100644 --- a/soc/renesas/rz/soc.yml +++ b/soc/renesas/rz/soc.yml @@ -35,6 +35,11 @@ family: - name: r9a09g057h44gbg cpuclusters: - name: cm33 + - name: rzv2n + socs: + - name: r9a09g056n48gbg + cpuclusters: + - name: cm33 - name: rzn2l socs: - name: r9a07g084m04gbg