boards: arm: add raytac_mdbt53v_db_40_nrf5340

Adds new raytac_mdbt53_db_40_nrf5340 board.

Signed-off-by: Stanley Huang <stanley@raytac.com>

boards/arm/raytac_mdbt53v_db_40_nrf5340/CMakeLists.txt

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+# SPDX-License-Identifier: Apache-2.0
+
+if ((CONFIG_BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP OR CONFIG_BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS)
+    AND CONFIG_BOARD_ENABLE_CPUNET)
+  zephyr_library()
+  zephyr_library_sources(raytac_mdbt53v_db_40_nrf5340_cpunet_reset.c)
+endif()

boards/arm/raytac_mdbt53v_db_40_nrf5340/Kconfig

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+# Ratac MDBT53V-DB-40 nRF5340 board configuration
+
+# Copyright (c) 2019 - 2021 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS
+
+config BOARD_ENABLE_DCDC_APP
+	bool "Application MCU DCDC converter"
+	select SOC_DCDC_NRF53X_APP
+	default y
+
+config BOARD_ENABLE_DCDC_NET
+	bool "Network MCU DCDC converter"
+	select SOC_DCDC_NRF53X_NET
+	default y
+
+config BOARD_ENABLE_DCDC_HV
+	bool "High Voltage DCDC converter"
+	select SOC_DCDC_NRF53X_HV
+	default y
+
+config BOARD_ENABLE_CPUNET
+	bool "NRF53 Network MCU"
+	select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \
+		$(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER))
+	help
+	  This option enables releasing the Network 'force off' signal, which
+	  as a consequence will power up the Network MCU during system boot.
+	  Additionally, the option allocates GPIO pins that will be used by UARTE
+	  of the Network MCU.
+	  Note: GPIO pin allocation can only be configured by the secure Application
+	  MCU firmware, so when this option is used with the non-secure version of
+	  the board, the application needs to take into consideration, that the
+	  secure firmware image must already have configured GPIO allocation for the
+	  Network MCU.
+	default y if (BT || NRF_802154_SER_HOST)
+
+config DOMAIN_CPUNET_BOARD
+	string
+	default "raytac_mdbt53v_db_40_nrf5340_cpunet"
+	depends on BOARD_ENABLE_CPUNET
+	help
+	  The board which will be used for CPUNET domain when creating a multi
+	  image application where one or more images should be located on
+	  another board. For example hci_rpmsg on the nRF5340_cpunet for
+	  Bluetooth applications.
+
+endif #  BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS
+
+config DOMAIN_CPUAPP_BOARD
+	string
+	default "raytac_mdbt53v_db_40_nrf5340_cpuapp"
+	depends on BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUNET
+	help
+	  The board which will be used for CPUAPP domain when creating a multi
+	  image application where one or more images should be located on
+	  another board.

boards/arm/raytac_mdbt53v_db_40_nrf5340/Kconfig.board

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+# Raytac MDBT53-DB-40 NRF5340 board configuration
+
+# Copyright (c) 2019-2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_NRF5340_CPUAPP_QKAA
+
+config BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP
+	bool "Raytac MDBT53V-DB-40 nRF5340 Application MCU"
+
+config BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS
+	bool "Raytac MDBT53V-DB-40 nRF5340 Application MCU non-secure"
+
+endif # SOC_NRF5340_CPUAPP_QKAA
+
+config BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUNET
+	bool "Raytac MDBT53V-DB-40 NRF5340 Network MCU"
+	depends on SOC_NRF5340_CPUNET_QKAA

boards/arm/raytac_mdbt53v_db_40_nrf5340/Kconfig.defconfig

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+# Raytac MDBT53V-DB-40 nRF5340 board configuration
+
+# Copyright (c) 2019-2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+if  BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS
+
+config BOARD
+	default "raytac_mdbt53v_db_40_nrf5340_cpuapp" if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS
+# By default, if we build for a Non-Secure version of the board,
+# enable building with TF-M as the Secure Execution Environment.
+config BUILD_WITH_TFM
+	default n if BOARD_BL5340_DVK_CPUAPP_NS
+
+if BUILD_WITH_TFM
+
+# By default, if we build with TF-M, instruct build system to
+# flash the combined TF-M (Secure) & Zephyr (Non Secure) image
+config TFM_FLASH_MERGED_BINARY
+	bool
+	default n
+
+endif # BUILD_WITH_TFM
+
+# Code Partition:
+#
+# For the secure version of the board the firmware is linked at the beginning
+# of the flash, or into the code-partition defined in DT if it is intended to
+# be loaded by MCUboot. If the secure firmware is to be combined with a non-
+# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always
+# be restricted to the size of its code partition.
+#
+# For the non-secure version of the board, the firmware
+# must be linked into the code-partition (non-secure) defined in DT, regardless.
+# Apply this configuration below by setting the Kconfig symbols used by
+# the linker according to the information extracted from DT partitions.
+
+# SRAM Partition:
+#
+# If the secure firmware is to be combined with a non-secure image
+# (TRUSTED_EXECUTION_SECURE=y), the secure FW image SRAM shall always
+# be restricted to the secure image SRAM partition (sram-secure-partition).
+# Otherwise (if TRUSTED_EXECUTION_SECURE is not set) the whole zephyr,sram
+# may be used by the image.
+#
+# For the non-secure version of the board, the firmware image SRAM is
+# always restricted to the allocated non-secure SRAM partition.
+#
+# Workaround for not being able to have commas in macro arguments
+DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition
+DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition
+
+if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE
+
+config FLASH_LOAD_SIZE
+	default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION))
+
+config SRAM_SIZE
+	default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM_PARTITION),0,K)
+
+endif # BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE
+
+if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS
+
+config FLASH_LOAD_OFFSET
+	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION))
+
+config FLASH_LOAD_SIZE
+	default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION))
+
+endif # BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS
+
+endif # BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS
+
+config BOARD
+	default "raytac_mdbt53v_dv_40_nrf5340_cpunet" if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUNET
+
+config IPM_NRFX
+	default IPM
+
+config MBOX_NRFX_IPC
+	default MBOX
+
+if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS
+
+choice BT_HCI_BUS_TYPE
+	default BT_RPMSG if BT
+endchoice
+
+config HEAP_MEM_POOL_SIZE
+	default 4096 if BT_RPMSG
+
+endif #  BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS
+
+if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUNET
+
+config BT_CTLR
+	default y if BT
+
+endif # BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUNET

boards/arm/raytac_mdbt53v_db_40_nrf5340/board.cmake

@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP OR CONFIG_BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS)
+  board_runner_args(jlink "--device=nrf5340_xxaa_app" "--speed=4000")
+endif()
+
+if(CONFIG_BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUNET)
+  board_runner_args(jlink "--device=nrf5340_xxaa_net" "--speed=4000")
+endif()
+
+include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

boards/arm/raytac_mdbt53v_db_40_nrf5340/doc/index.rst

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+.. _raytac_mdbt53v_db_40_nrf5340:
+
+Raytac MDBT53V-DB-40
+####################
+
+Overview
+********
+
+Raytac MDBT53V-DB-40 demo board is a development board based on the Raytac MDBT53V-1M module,
+using Nordic Semiconductor nRF5340 ARM Cortex-M33 SoC. Its design concept is to connect all
+of the module's pins to 2.54mm pin headers. It is convenient for developers to verify whether
+the modules are connected to other peripheral devices or sensors as a tool for software development.
+
+The nRF5340 inside the MDBT53V-1M module is a
+dual-core SoC based on the Arm® Cortex®-M33 architecture, with:
+
+* a full-featured Arm Cortex-M33F core with DSP instructions, FPU, and
+  Armv8-M Security Extension, running at up to 128 MHz, referred to as
+  the **application core**
+* a secondary Arm Cortex-M33 core, with a reduced feature set, running
+  at a fixed 64 MHz, referred to as the **network core**.
+
+The raytac_mdbt53v_db_40_nrf5340_cpuapp build target provides support for the application
+core on the nRF5340 SoC. The raytac_mdbt53v_db_40_nrf5340_cpuapp build target provides
+support for the network core on the nRF5340 SoC.
+
+.. note::
+   Trusted Firmware-M (TF-M) and building the ``ns`` target is not supported for this board.
+
+nRF5340 SoC provides support for the following devices:
+
+* :abbr:`ADC (Analog to Digital Converter)`
+* CLOCK
+* FLASH
+* :abbr:`GPIO (General Purpose Input Output)`
+* :abbr:`IDAU (Implementation Defined Attribution Unit)`
+* :abbr:`I2C (Inter-Integrated Circuit)`
+* :abbr:`MPU (Memory Protection Unit)`
+* :abbr:`NVIC (Nested Vectored Interrupt Controller)`
+* :abbr:`PWM (Pulse Width Modulation)`
+* RADIO (Bluetooth Low Energy and 802.15.4)
+* :abbr:`RTC (nRF RTC System Clock)`
+* Segger RTT (RTT Console)
+* :abbr:`SPI (Serial Peripheral Interface)`
+* :abbr:`UARTE (Universal asynchronous receiver-transmitter)`
+* :abbr:`WDT (Watchdog Timer)`
+
+.. figure:: img/MDBT53V-DB-40.jpg
+     :width: 442px
+     :align: center
+     :alt: MDBT53V-DB-40
+
+     MDBT53V-DB-40 (Credit: Raytac Corporation)
+
+More information about the board can be found at the `MDBT53V-DB-40 website`_.
+The `MDBT53V-DB-40 Specification`_ contains the demo board's datasheet.
+The `MDBT53V-DB-40 Schematic`_ contains the demo board's schematic.
+
+Hardware
+********
+- Module Demo Board build by MDBT53V-1M
+- Nordic nRF5340 SoC Solution
+- A recommnded 3rd-party module by Nordic Semiconductor.
+- Dual-core Arm® Cortex® M33
+- 1MB/256KB Flash Memory; 512kB/ 64kB RAM
+- Supports BT5 Long Range Features
+- Bluetooth specification v5.2
+- Supports BT5 Long Range Features
+- Supports Bluetooth Direction Finding & Mesh
+- Supports Bluetooth low energy audio
+- Cerifications: FCC, IC, CE, Telec(MIC), KC, SRRC, NCC, RCM, WPC
+- RoHs & Reach Compiant.
+- 25 GPIO
+- Chip Antenna
+- Interfaces: SPI, UART, I2C, I2S, PWM, ADC, and NFC
+- Highly flexible multiprotocol SoC ideally suited for Bluetooth® Low Energy, ANT+, Zigbee, Thread (802.15.4) ultra low-power wireless applications.
+- 1 User LEDs
+- 3 User buttons
+- 1 Mini USB connector for power supply
+- SWD connector for FW programing
+- J-Link interface for FW programing
+
+Supported Features
+==================
+
+The raytac_mdbt53v_db_40_nrf5340_cpuapp board configuration supports the following
+hardware features:
+
++-----------+------------+----------------------+
+| Interface | Controller | Driver/Component     |
++===========+============+======================+
+| ADC       | on-chip    | adc                  |
++-----------+------------+----------------------+
+| CLOCK     | on-chip    | clock_control        |
++-----------+------------+----------------------+
+| FLASH     | on-chip    | flash                |
++-----------+------------+----------------------+
+| GPIO      | on-chip    | gpio                 |
++-----------+------------+----------------------+
+| I2C(M)    | on-chip    | i2c                  |
++-----------+------------+----------------------+
+| MPU       | on-chip    | arch/arm             |
++-----------+------------+----------------------+
+| NVIC      | on-chip    | arch/arm             |
++-----------+------------+----------------------+
+| PWM       | on-chip    | pwm                  |
++-----------+------------+----------------------+
+| RTC       | on-chip    | system clock         |
++-----------+------------+----------------------+
+| SPI(M/S)  | on-chip    | spi                  |
++-----------+------------+----------------------+
+| UARTE     | on-chip    | serial               |
++-----------+------------+----------------------+
+| WDT       | on-chip    | watchdog             |
++-----------+------------+----------------------+
+
+The raytac_mdbt53v_db_40_nrf5340_cpunet board configuration supports the following
+hardware features:
+
++-----------+------------+----------------------+
+| Interface | Controller | Driver/Component     |
++===========+============+======================+
+| CLOCK     | on-chip    | clock_control        |
++-----------+------------+----------------------+
+| FLASH     | on-chip    | flash                |
++-----------+------------+----------------------+
+| GPIO      | on-chip    | gpio                 |
++-----------+------------+----------------------+
+| I2C(M)    | on-chip    | i2c                  |
++-----------+------------+----------------------+
+| MPU       | on-chip    | arch/arm             |
++-----------+------------+----------------------+
+| NVIC      | on-chip    | arch/arm             |
++-----------+------------+----------------------+
+| RADIO     | on-chip    | Bluetooth,           |
+|           |            | ieee802154           |
++-----------+------------+----------------------+
+| RTC       | on-chip    | system clock         |
++-----------+------------+----------------------+
+| SPI(M/S)  | on-chip    | spi                  |
++-----------+------------+----------------------+
+| UARTE     | on-chip    | serial               |
++-----------+------------+----------------------+
+| WDT       | on-chip    | watchdog             |
++-----------+------------+----------------------+
+
+Other hardware features have not been enabled yet for this board.
+See `MDBT53V-DB-40 website`_ and `MDBT53V-DB-40 Specification`_
+for a complete list of Raytac MDBT53V-DB-40 board hardware features.
+
+Connections and IOs
+===================
+
+LED
+---
+
+* LED1 (green) = P0.31
+
+Push buttons
+------------
+
+* BUTTON1 = SW1 = P1.13
+* BUTTON2 = SW2 = P0.25
+* BUTTON3 = SW3 = P0.26
+
+HSPI
+----
+* MOSI = P0.9
+* MISO = P0.10
+* SCK = P0.8
+* CSN = P0.11
+* DCX = P0.12
+
+QSPI
+----
+* SCK = P0.17
+* CSN = P0.18
+* DATA0 = P0.13
+* DATA1 = P0.14
+* DATA2 = P0.15
+* DATA3 = P0.16
+
+Security components
+===================
+
+- Implementation Defined Attribution Unit (`IDAU`_) on the application core.
+  The IDAU is implemented with the System Protection Unit and is used to
+  define secure and non-secure memory maps.  By default, all of the memory
+  space  (Flash, SRAM, and peripheral address space) is defined to be secure
+  accessible only.
+- Secure boot.
+
+Programming and Debugging
+*************************
+
+nRF5340 application core supports the Armv8-M Security Extension.
+Applications built for the raytac_mdbt53v_db_40_nrf5340_cpuapp board by
+default boot in the Secure state.
+
+nRF5340 network core does not support the Armv8-M Security Extension.
+nRF5340 IDAU may configure bus accesses by the nRF5340 network core
+to have Secure attribute set; the latter allows to build and run
+Secure only applications on the nRF5340 SoC.
+
+Applications for the ``raytac_mdbt53v_db_40_nrf5340`` board configuration can be
+built, flashed, and debugged in the usual way. See :ref:`build_an_application` and
+:ref:`application_run` for more details on building and running.
+
+.. note::
+   Flashing and Debugging Zephyr onto the raytac_mdbt53v_db_40_nrf5340 board
+   requires an	external J-Link programmer. The programmer is attached to the J1
+   or J9 SWD connector.
+
+
+Flashing
+========
+
+Follow the instructions in the :ref:`nordic_segger` page to install
+and configure all the necessary software. Further information can be
+found in :ref:`nordic_segger_flashing`. Then build and flash
+applications as usual (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+Here is an example for the :ref:`hello_world` application.
+
+Use a USB to TTL converter to connect the computer and raytac_mdbt53v_db_40_nrf5340
+J13 connector pin 8(RX), 9(TX) and GND. Then run your favorite terminal program to listen for output.
+
+.. code-block:: console
+
+   $ minicom -D <tty_device> -b 115200
+
+Replace :code:`<tty_device>` with the port where the USB to TTL converter
+can be found. For example, under Linux, :code:`/dev/ttyUSB0`.
+
+Then build and flash the application in the usual way.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: raytac_mdbt53v_db_40_nrf5340
+   :goals: build flash
+
+Debugging
+=========
+
+The ``raytac_mdbt53v_db_40_nrf5340`` board does not have an on-board-J-Link debug IC,
+however, instructions from the :ref:`nordic_segger` page also apply to this board.
+Use the Debug out connector of nRF52x DK to connect to the J1 connector, and use SEGGER
+J-Link OB IF to debug.
+
+
+References
+**********
+
+.. _IDAU:
+   https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau
+.. _MDBT53V-DB-40 website:
+	https://www.raytac.com/product/ins.php?index_id=140
+.. _MDBT53V-DB-40 Specification:
+	https://www.raytac.com/download/index.php?index_id=62
+.. _MDBT53V-DB-40 Schematic:
+	https://www.raytac.com/upload/catalog_b/f2c33d52dca8cd6546c95938bc0cb295.jpg
+.. _J-Link Software and documentation pack:
+	https://www.segger.com/jlink-software.html

boards/arm/raytac_mdbt53v_db_40_nrf5340/pre_dt_board.cmake

@@ -0,0 +1,8 @@
+# Copyright (c) 2021 Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+# Suppress "unique_unit_address_if_enabled" to handle the following overlaps:
+# - flash-controller@39000 & kmu@39000
+# - power@5000 & clock@5000
+# - /reserved-memory/image@20000000 & /reserved-memory/image_s@20000000
+list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled")

boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp.dts

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2023 Raytac Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <nordic/nrf5340_cpuapp_qkaa.dtsi>
+#include "raytac_mdbt53v_db_40_nrf5340_cpuapp_common.dts"
+
+/ {
+	model = "Raytac MDBT53V-DB-40 NRF5340 Application";
+	compatible = "raytac,raytac-mdbt53v-db-40-nrf5340-cpuapp";
+
+	chosen {
+		zephyr,sram = &sram0_image;
+		zephyr,flash = &flash0;
+		zephyr,code-partition = &slot0_partition;
+		zephyr,sram-secure-partition = &sram0_s;
+		zephyr,sram-non-secure-partition = &sram0_ns;
+	};
+};

boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp.yaml

@@ -0,0 +1,20 @@
+identifier: raytac_mdbt53v_db_40_nrf5340_cpuapp
+name: RAYTAC-MDBT53V-DB-40-NRF5340-application-MCU
+type: mcu
+arch: arm
+toolchain:
+  - gnuarmemb
+  - xtools
+  - zephyr
+ram: 448
+flash: 1024
+supported:
+  - counter
+  - gpio
+  - i2c
+  - i2s
+  - pwm
+  - qspi
+  - spi
+  - watchdog
+  - netif:openthread

boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_common-pinctrl.dtsi

@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2023 Raytac Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	i2c1_default: i2c1_default {
+		group1 {
+			psels = <NRF_PSEL(TWIM_SDA, 1, 2)>,
+				<NRF_PSEL(TWIM_SCL, 1, 3)>;
+		};
+	};
+
+	i2c1_sleep: i2c1_sleep {
+		group1 {
+			psels = <NRF_PSEL(TWIM_SDA, 1, 2)>,
+				<NRF_PSEL(TWIM_SCL, 1, 3)>;
+			low-power-enable;
+		};
+	};
+
+	uart0_default: uart0_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 0, 31)>,
+				<NRF_PSEL(UART_RX, 1, 11)>,
+				<NRF_PSEL(UART_RTS, 1, 13)>,
+				<NRF_PSEL(UART_CTS, 1, 12)>;
+		};
+	};
+
+	uart0_sleep: uart0_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 0, 31)>,
+				<NRF_PSEL(UART_RX, 1, 11)>,
+				<NRF_PSEL(UART_RTS, 1, 13)>,
+				<NRF_PSEL(UART_CTS, 1, 12)>;
+			low-power-enable;
+		};
+	};
+
+	pwm0_default: pwm0_default {
+		group1 {
+			psels = <NRF_PSEL(PWM_OUT0, 0, 28)>;
+		};
+	};
+
+	pwm0_sleep: pwm0_sleep {
+		group1 {
+			psels = <NRF_PSEL(PWM_OUT0, 0, 28)>;
+			low-power-enable;
+		};
+	};
+
+	qspi_default: qspi_default {
+		group1 {
+			psels = <NRF_PSEL(QSPI_SCK, 0, 17)>,
+				<NRF_PSEL(QSPI_IO0, 0, 13)>,
+				<NRF_PSEL(QSPI_IO1, 0, 14)>,
+				<NRF_PSEL(QSPI_IO2, 0, 15)>,
+				<NRF_PSEL(QSPI_IO3, 0, 16)>,
+				<NRF_PSEL(QSPI_CSN, 0, 18)>;
+		};
+	};
+
+	qspi_sleep: qspi_sleep {
+		group1 {
+			psels = <NRF_PSEL(QSPI_SCK, 0, 17)>,
+				<NRF_PSEL(QSPI_IO0, 0, 13)>,
+				<NRF_PSEL(QSPI_IO1, 0, 14)>,
+				<NRF_PSEL(QSPI_IO2, 0, 15)>,
+				<NRF_PSEL(QSPI_IO3, 0, 16)>,
+				<NRF_PSEL(QSPI_CSN, 0, 18)>;
+			low-power-enable;
+		};
+	};
+
+	spi4_default: spi4_default {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 0, 8)>,
+				<NRF_PSEL(SPIM_MISO, 0, 10)>,
+				<NRF_PSEL(SPIM_MOSI, 0, 9)>;
+		};
+	};
+
+	spi4_sleep: spi4_sleep {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 0, 8)>,
+				<NRF_PSEL(SPIM_MISO, 0, 10)>,
+				<NRF_PSEL(SPIM_MOSI, 0, 9)>;
+			low-power-enable;
+		};
+	};
+
+};

boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_common.dts

@@ -0,0 +1,186 @@
+/*
+ * Copyright (c) 2023 Raytac Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "raytac_mdbt53v_db_40_nrf5340_cpuapp_common-pinctrl.dtsi"
+
+/ {
+
+	chosen {
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,uart-mcumgr = &uart0;
+		zephyr,bt-mon-uart = &uart0;
+		zephyr,bt-c2h-uart = &uart0;
+		zephyr,bt-hci-rpmsg-ipc = &ipc0;
+		nordic,802154-spinel-ipc = &ipc0;
+		zephyr,ieee802154 = &ieee802154;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		led0: led_0 {
+			gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
+			label = "Green LED 0";
+		};
+	};
+
+	pwmleds {
+		compatible = "pwm-leds";
+		pwm_led0: pwm_led_0 {
+			pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+		button0: button_0 {
+			gpios = <&gpio0 24 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Push button 1";
+		};
+		button1: button_1 {
+			gpios = <&gpio0 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Push button 2";
+		};
+		button2: button_2 {
+			gpios = <&gpio0 23 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Push button 3";
+		};
+	};
+
+	gpio_fwd: nrf-gpio-forwarder {
+		compatible = "nordic,nrf-gpio-forwarder";
+		status = "okay";
+		uart {
+			gpios = <&gpio1 1 0>, <&gpio1 0 0>, <&gpio0 11 0>, <&gpio0 10 0>;
+		};
+	};
+
+	/* These aliases are provided for compatibility with samples */
+	aliases {
+		led0 = &led0;
+		pwm-led0 = &pwm_led0;
+		sw0 = &button0;
+		sw1 = &button1;
+		sw2 = &button2;
+		bootloader-led0 = &led0;
+		mcuboot-button0 = &button0;
+		mcuboot-led0 = &led0;
+		watchdog0 = &wdt0;
+	};
+};
+
+&adc {
+	status = "okay";
+};
+
+&gpiote {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&i2c1 {
+	compatible = "nordic,nrf-twim";
+	status = "okay";
+	pinctrl-0 = <&i2c1_default>;
+	pinctrl-1 = <&i2c1_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+&uart0 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart0_default>;
+	pinctrl-1 = <&uart0_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+&pwm0 {
+	status = "okay";
+	pinctrl-0 = <&pwm0_default>;
+	pinctrl-1 = <&pwm0_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+&qspi {
+	status = "okay";
+	pinctrl-0 = <&qspi_default>;
+	pinctrl-1 = <&qspi_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+&spi4 {
+	compatible = "nordic,nrf-spim";
+	status = "okay";
+	cs-gpios = <&gpio0 11 0>;
+	pinctrl-0 = <&spi4_default>;
+	pinctrl-1 = <&spi4_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+&flash0 {
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x00000000 0x00010000>;
+		};
+		slot0_partition: partition@10000 {
+			label = "image-0";
+		};
+		slot0_ns_partition: partition@50000 {
+			label = "image-0-nonsecure";
+		};
+		slot1_partition: partition@80000 {
+			label = "image-1";
+		};
+		slot1_ns_partition: partition@c0000 {
+			label = "image-1-nonsecure";
+		};
+		/* 0xf0000 to 0xf7fff reserved for TF-M partitions */
+		storage_partition: partition@f8000 {
+			label = "storage";
+			reg = <0x000f8000 0x00008000>;
+		};
+	};
+};
+
+&ieee802154 {
+	status = "okay";
+};
+
+/ {
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		sram0_image: image@20000000 {
+			/* Zephyr image(s) memory */
+		};
+
+		sram0_s: image_s@20000000 {
+			/* Secure image memory */
+		};
+
+		sram0_ns: image_ns@20040000 {
+			/* Non-Secure image memory */
+		};
+	};
+};
+
+/* Include partition configuration file */
+#include "raytac_mdbt53v_db_40_nrf5340_cpuapp_partition_conf.dts"

boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_defconfig

@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SOC_SERIES_NRF53X=y
+CONFIG_SOC_NRF5340_CPUAPP_QKAA=y
+CONFIG_BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP=y
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable hardware stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+# Enable TrustZone-M
+CONFIG_ARM_TRUSTZONE_M=y
+
+# enable GPIO
+CONFIG_GPIO=y
+
+# Enable uart driver
+CONFIG_SERIAL=y
+
+# enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+CONFIG_PINCTRL=y

boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.dts

@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2023 Raytac Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <nordic/nrf5340_cpuappns_qkaa.dtsi>
+#include "raytac_mdbt53v_db_40_nrf5340_cpuapp_common.dts"
+
+/ {
+	model = "Raytac MDBT53V-DB-40 NRF5340 Application";
+	compatible = "raytac,raytac-mdbt53v-db-40-nrf5340-cpuapp";
+
+	chosen {
+		zephyr,sram = &sram0_ns;
+		zephyr,flash = &flash0;
+		zephyr,code-partition = &slot0_ns_partition;
+	};
+};

boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.yaml

@@ -0,0 +1,16 @@
+identifier: raytac_mdbt53v_db_40_nrf5340_cpuapp_ns
+name: RAYTAC-MDBT53V-DB-40-NRF52840-application-MCU-Non-Secure
+type: mcu
+arch: arm
+toolchain:
+  - gnuarmemb
+  - xtools
+  - zephyr
+ram: 192
+flash: 192
+supported:
+  - i2c
+  - pwm
+  - watchdog
+  - netif:openthread
+  - gpio

boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns_defconfig

@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SOC_SERIES_NRF53X=y
+CONFIG_SOC_NRF5340_CPUAPP_QKAA=y
+CONFIG_BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS=y
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable hardware stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+# Enable TrustZone-M
+CONFIG_ARM_TRUSTZONE_M=y
+
+# This Board implies building Non-Secure firmware
+CONFIG_TRUSTED_EXECUTION_NONSECURE=y
+
+# enable GPIO
+CONFIG_GPIO=y
+
+# Enable uart driver
+CONFIG_SERIAL=y
+
+# enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+CONFIG_PINCTRL=y

boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_partition_conf.dts

@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2023 Raytac Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Default Flash planning for raytac_mdbt53v_db_40_nrf5340 CPUAPP (Application MCU).
+ *
+ * Zephyr build for nRF5340 with ARM TrustZone-M support,
+ * implies building Secure and Non-Secure Zephyr images.
+ *
+ * Secure image will be placed, by default, in flash0
+ * (or in slot0, if MCUboot is present).
+ * Secure image will use sram0 for system memory.
+ *
+ * Non-Secure image will be placed in slot0_ns, and use
+ * sram0_ns for system memory.
+ *
+ * Note that the Secure image only requires knowledge of
+ * the beginning of the Non-Secure image (not its size).
+ */
+
+&slot0_partition {
+	reg = <0x00010000 0x40000>;
+};
+
+&slot0_ns_partition {
+	reg = <0x00050000 0x30000>;
+};
+
+&slot1_partition {
+	reg = <0x00080000 0x40000>;
+};
+
+&slot1_ns_partition {
+	reg = <0x000c0000 0x30000>;
+};
+
+/* Default SRAM planning when building for nRF5340 with
+ * ARM TrustZone-M support
+ * - Lowest 256 kB SRAM allocated to Secure image (sram0_s)
+ * - Middle 192 kB allocated to Non-Secure image (sram0_ns)
+ * - Upper 64 kB SRAM allocated as Shared memory (sram0_shared)
+ *   (see raytac_mdbt53v_db_40_nrf5340_shared_sram_planning_conf.dts)
+ */
+&sram0_image {
+	reg = <0x20000000 DT_SIZE_K(448)>;
+};
+
+&sram0_s {
+	reg = <0x20000000 0x40000>;
+};
+
+&sram0_ns {
+	reg = <0x20040000 0x30000>;
+};
+
+/* Include shared RAM configuration file */
+#include "raytac_mdbt53v_db_40_nrf5340_shared_sram_planning_conf.dts"

boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpunet-pinctrl.dtsi

@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2023 Raytac Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	uart0_default: uart0_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 0, 31)>,
+				<NRF_PSEL(UART_RTS, 1, 13)>,
+			    <NRF_PSEL(UART_RX, 1, 11)>,
+				<NRF_PSEL(UART_CTS, 1, 12)>;
+		};
+	};
+
+	uart0_sleep: uart0_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 0, 31)>,
+				<NRF_PSEL(UART_RX, 1, 13)>,
+				<NRF_PSEL(UART_RTS, 1, 11)>,
+				<NRF_PSEL(UART_CTS, 1, 12)>;
+			low-power-enable;
+		};
+	};
+
+};

boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpunet.dts

@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2023 Raytac Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <nordic/nrf5340_cpunet_qkaa.dtsi>
+#include "raytac_mdbt53v_db_40_nrf5340_cpunet-pinctrl.dtsi"
+#include "raytac_mdbt53v_db_40_nrf5340_cpunet_common.dts"
+/ {
+	model = "Raytac MDBT53V-DB-40 NRF5340 Network";
+	compatible = "raytac,raytac-mdbt53v-db-40-nrf5340-cpunet";
+
+	chosen {
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,uart-mcumgr = &uart0;
+		zephyr,bt-mon-uart = &uart0;
+		zephyr,bt-c2h-uart = &uart0;
+		zephyr,sram = &sram1;
+		zephyr,flash = &flash1;
+		zephyr,code-partition = &slot0_partition;
+		zephyr,bt-hci-rpmsg-ipc = &ipc0;
+	};
+
+
+	/* These aliases are provided for compatibility with samples */
+	aliases {
+		watchdog0 = &wdt0;
+	};
+};
+
+&uart0 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart0_default>;
+	pinctrl-1 = <&uart0_sleep>;
+	pinctrl-names = "default", "sleep";
+};

boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpunet.yaml

@@ -0,0 +1,20 @@
+# Raytac MDBT53V_DB_40_NRF5340 board configuration
+
+# Copyright (c) 2023 Raytac Corporation
+# SPDX-License-Identifier: Apache-2.0
+identifier: raytac_mdbt53v_db_40_nrf5340_cpunet
+name: RAYTAC MDBT53V-DB-40-NRF5340-network-MCU
+type: mcu
+arch: arm
+toolchain:
+  - gnuarmemb
+  - xtools
+  - zephyr
+ram: 64
+flash: 256
+supported:
+  - watchdog
+  - gpio
+  - i2c
+  - spi
+  - uart

boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpunet_common.dts

@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2023 Raytac Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <nordic/nrf5340_cpunet_qkaa.dtsi>
+
+&gpiote {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&timer0 {
+	status = "okay";
+};
+
+&timer1 {
+	status = "okay";
+};
+
+&timer2 {
+	status = "okay";
+};
+
+&flash1 {
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x00000000 0xc000>;
+		};
+		slot0_partition: partition@c000 {
+			label = "image-0";
+			reg = <0x0000C000 0x17000>;
+		};
+		slot1_partition: partition@23000 {
+			label = "image-1";
+			reg = <0x00023000 0x17000>;
+		};
+		storage_partition: partition@3a000 {
+			label = "storage";
+			reg = <0x0003a000 0x6000>;
+		};
+	};
+};
+
+/* Include shared RAM configuration file */
+#include "raytac_mdbt53v_db_40_nrf5340_shared_sram_planning_conf.dts"

boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpunet_defconfig

@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SOC_SERIES_NRF53X=y
+CONFIG_SOC_NRF5340_CPUNET_QKAA=y
+CONFIG_BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUNET=y
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable hardware stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+# enable GPIO
+CONFIG_GPIO=y
+
+# Enable uart driver
+CONFIG_SERIAL=y
+
+# enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+CONFIG_PINCTRL=y

boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpunet_reset.c

@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2019-2021 Nordic Semiconductor ASA.
+ * Copyright (c) 2023 Raytac Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/init.h>
+#include <zephyr/logging/log.h>
+
+#include <soc.h>
+
+LOG_MODULE_REGISTER(raytac_mdbt53v_db_40_nrf5340_cpuapp, CONFIG_LOG_DEFAULT_LEVEL);
+
+#if defined(CONFIG_BT_CTLR_DEBUG_PINS_CPUAPP)
+#include <../subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/debug.h>
+#else
+#define DEBUG_SETUP()
+#endif
+
+static void remoteproc_mgr_config(void)
+{
+#if !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) || defined(CONFIG_BUILD_WITH_TFM)
+	/* Route Bluetooth Controller Debug Pins */
+	DEBUG_SETUP();
+#endif /* !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) || defined(CONFIG_BUILD_WITH_TFM) */
+
+#if !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE)
+	/* Retain nRF5340 Network MCU in Secure domain (bus
+	 * accesses by Network MCU will have Secure attribute set).
+	 */
+	NRF_SPU->EXTDOMAIN[0].PERM = 1 << 4;
+#endif /* !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE) */
+}
+
+static int remoteproc_mgr_boot(const struct device *dev)
+{
+
+	/* Secure domain may configure permissions for the Network MCU. */
+	remoteproc_mgr_config();
+
+#if !defined(CONFIG_TRUSTED_EXECUTION_SECURE)
+	/*
+	 * Building Zephyr with CONFIG_TRUSTED_EXECUTION_SECURE=y implies
+	 * building also a Non-Secure image. The Non-Secure image will, in
+	 * this case do the remainder of actions to properly configure and
+	 * boot the Network MCU.
+	 */
+
+	/* Release the Network MCU, 'Release force off signal' */
+	NRF_RESET->NETWORK.FORCEOFF = RESET_NETWORK_FORCEOFF_FORCEOFF_Release;
+
+	LOG_DBG("Network MCU released.");
+#endif /* !CONFIG_TRUSTED_EXECUTION_SECURE */
+
+	return 0;
+}
+
+SYS_INIT(remoteproc_mgr_boot, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);

boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_shared_sram_planning_conf.dts

@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2023 Raytac Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Default shared SRAM planning when building for nRF5340.
+ * This file is included by both nRF5340 CPUAPP (Application MCU)
+ * and nRF5340 CPUNET (Network MCU).
+ * - 64 kB SRAM allocated as Shared memory (sram0_shared)
+ * - Region defined after the image SRAM of Application MCU
+ */
+
+/ {
+	chosen {
+		/* shared memory reserved for the inter-processor communication */
+		zephyr,ipc_shm = &sram0_shared;
+	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		sram0_shared: memory@20070000 {
+			/* SRAM allocated to shared memory */
+			reg = <0x20070000 0x10000>;
+		};
+	};
+};

samples/net/wpan_serial/sample.yaml

@@ -4,15 +4,13 @@ sample:
 common:
   depends_on: usb_device
   harness: net
-  tags:
-    - net
-    - usb
-    - ieee802154
+  tags: usb ieee802154
   platform_exclude: pinnacle_100_dvk
 tests:
   sample.net.wpan.serial:
     filter: dt_chosen_enabled("zephyr,ieee802154")
-    platform_exclude: thingy53_nrf5340_cpuapp_ns
-  sample.net.wpan.serial.frdm_cr20a:
+    platform_exclude: thingy53_nrf5340_cpuapp_ns raytac_mdbt53_db_40_nrf5340_cpuapp_ns
+                      raytac_mdbt53_db_40_nrf5340_cpuapp
+  sample.net.wpan_serial.frdm_cr20a:
     extra_args: SHIELD=frdm_cr20a
     platform_allow: frdm_k64f

samples/net/wpanusb/sample.yaml

@@ -3,16 +3,14 @@ sample:
   name: wpanusb
 common:
   depends_on: usb_device
-  tags:
-    - net
-    - ieee802154
-    - usb
+  tags: net ieee802154 usb
   harness: net
   platform_exclude: pinnacle_100_dvk
 tests:
   sample.net.wpanusb:
     filter: dt_chosen_enabled("zephyr,ieee802154")
-    platform_exclude: thingy53_nrf5340_cpuapp_ns
+    platform_exclude: thingy53_nrf5340_cpuapp_ns raytac_mdbt53_db_40_nrf5340_cpuapp_ns
+                      raytac_mdbt53_db_40_nrf5340_cpuapp
   sample.net.wpanusb_frdm_cr20a:
     extra_args: SHIELD=frdm_cr20a
     platform_allow: frdm_k64f