diff --git a/boards/arm/nucleo_h723zg/nucleo_h723zg.dts b/boards/arm/nucleo_h723zg/nucleo_h723zg.dts
index 8bb0733f70e..6f931a59daf 100644
--- a/boards/arm/nucleo_h723zg/nucleo_h723zg.dts
+++ b/boards/arm/nucleo_h723zg/nucleo_h723zg.dts
@@ -62,6 +62,33 @@
 	};
 };
 
+&clk_hse {
+	hse-bypass;
+	clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
+	status = "okay";
+};
+
+&pll {
+	div-m = <4>;
+	mul-n = <275>;
+	div-p = <1>;
+	div-q = <4>;
+	div-r = <2>;
+	clocks = <&clk_hse>;
+	status = "okay";
+};
+
+&rcc {
+	clocks = <&pll>;
+	clock-frequency = <DT_FREQ_M(550)>;
+	d1cpre = <1>;
+	hpre = <2>;    /* HCLK: 275   MHz */
+	d1ppre = <2>;  /* APB1: 137.5 MHz */
+	d2ppre1 = <2>; /* APB2: 137.5 MHz */
+	d2ppre2 = <2>; /* APB3: 137.5 MHz */
+	d3ppre = <2>;  /* APB4: 137.5 MHz */
+};
+
 &usart3 {
 	pinctrl-0 = <&usart3_tx_pd8 &usart3_rx_pd9>;
 	current-speed = <115200>;
diff --git a/boards/arm/nucleo_h723zg/nucleo_h723zg_defconfig b/boards/arm/nucleo_h723zg/nucleo_h723zg_defconfig
index 742f3906dd8..ada15918fae 100644
--- a/boards/arm/nucleo_h723zg/nucleo_h723zg_defconfig
+++ b/boards/arm/nucleo_h723zg/nucleo_h723zg_defconfig
@@ -2,7 +2,6 @@
 
 CONFIG_SOC_SERIES_STM32H7X=y
 CONFIG_SOC_STM32H723XX=y
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=550000000
 
 CONFIG_BOARD_NUCLEO_H723ZG=y
 
@@ -25,37 +24,5 @@ CONFIG_PINMUX=y
 # Enable GPIO
 CONFIG_GPIO=y
 
-# Clock Configuration
+# Enable Clock
 CONFIG_CLOCK_CONTROL=y
-
-CONFIG_CLOCK_STM32_D1CPRE=1
-
-# HCLK: 275MHz
-CONFIG_CLOCK_STM32_HPRE=2
-
-# APB1: 137.5MHz
-CONFIG_CLOCK_STM32_D2PPRE1=2
-
-# APB2: 137.5MHz
-CONFIG_CLOCK_STM32_D2PPRE2=2
-
-# APB3: 137.5MHz
-CONFIG_CLOCK_STM32_D1PPRE=2
-
-# APB4: 137.5MHz
-CONFIG_CLOCK_STM32_D3PPRE=2
-
-# STLINK provides 8MHz clock input
-CONFIG_CLOCK_STM32_HSE_CLOCK=8000000
-CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
-
-# Use HSE (bypass) as PLL input
-CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
-CONFIG_CLOCK_STM32_HSE_BYPASS=y
-
-# Produce 550MHz clock at PLL1 output
-CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4
-CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=275
-CONFIG_CLOCK_STM32_PLL_P_DIVISOR=1
-CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4
-CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2