driver: dmamux: enable clocks only if node has clocks property defined
Not all STM32 Series can enable a dedicated clock for dmamux. In stm32g0 series for example the clock is enabled automatically as long as either DMA1 or DMA2 is enabled. This commit changes dmamux driver to cope with socs that don't have defined a clocks property. Therefore it moves the config(and data) struct into the c file to be able to use DT_INST_NODE_HAS_PROP macro. Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit is contained in:
parent
38f993b886
commit
73374fbfa9
2 changed files with 29 additions and 19 deletions
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@ -26,6 +26,25 @@ LOG_MODULE_REGISTER(dmamux_stm32, CONFIG_DMA_LOG_LEVEL);
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#define DT_DRV_COMPAT st_stm32_dmamux
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#define DT_DRV_COMPAT st_stm32_dmamux
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/* the table of all the dmamux channel */
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struct dmamux_stm32_data {
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void *callback_arg;
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void (*dmamux_callback)(void *arg, uint32_t id,
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int error_code);
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};
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/* this is the configuration of the dmamux IP */
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struct dmamux_stm32_config {
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#if DT_INST_NODE_HAS_PROP(0, clocks)
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struct stm32_pclken pclken;
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#endif
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uint32_t base;
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uint8_t channel_nb; /* total nb of channels */
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uint8_t gen_nb; /* total nb of Request generator */
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uint8_t req_nb; /* total nb of Peripheral Request inputs */
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const struct dmamux_stm32_channel *mux_channels;
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};
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int dmamux_stm32_configure(const struct device *dev, uint32_t id,
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int dmamux_stm32_configure(const struct device *dev, uint32_t id,
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struct dma_config *config)
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struct dma_config *config)
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{
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{
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@ -156,6 +175,7 @@ int dmamux_stm32_get_status(const struct device *dev, uint32_t id,
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static int dmamux_stm32_init(const struct device *dev)
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static int dmamux_stm32_init(const struct device *dev)
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{
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{
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#if DT_INST_NODE_HAS_PROP(0, clocks)
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const struct dmamux_stm32_config *config = dev->config;
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const struct dmamux_stm32_config *config = dev->config;
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const struct device *clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
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const struct device *clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
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@ -164,6 +184,7 @@ static int dmamux_stm32_init(const struct device *dev)
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LOG_ERR("clock op failed\n");
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LOG_ERR("clock op failed\n");
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return -EIO;
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return -EIO;
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}
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}
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#endif /* DT_INST_NODE_HAS_PROP(0, clocks) */
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/* DMAs assigned to DMAMUX channels at build time might not be ready. */
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/* DMAs assigned to DMAMUX channels at build time might not be ready. */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(dma1), okay)
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(dma1), okay)
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@ -230,6 +251,13 @@ static const struct dma_driver_api dma_funcs = {
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#define DMAMUX_CHANNELS_INIT_1(count) \
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#define DMAMUX_CHANNELS_INIT_1(count) \
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UTIL_LISTIFY(count, INIT_DMAMUX_1_CHANNEL)
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UTIL_LISTIFY(count, INIT_DMAMUX_1_CHANNEL)
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#define DMAMUX_CLOCK_INIT(index) \
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COND_CODE_1(DT_INST_NODE_HAS_PROP(index, clocks), \
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(.pclken = { .bus = DT_INST_CLOCKS_CELL(index, bus), \
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.enr = DT_INST_CLOCKS_CELL(index, bits)},), \
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())
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#define DMAMUX_INIT(index) \
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#define DMAMUX_INIT(index) \
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static const struct dmamux_stm32_channel \
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static const struct dmamux_stm32_channel \
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dmamux_stm32_channels_##index[DT_INST_PROP(index, dma_channels)] = { \
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dmamux_stm32_channels_##index[DT_INST_PROP(index, dma_channels)] = { \
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@ -237,8 +265,7 @@ static const struct dmamux_stm32_channel \
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}; \
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}; \
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\
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\
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const struct dmamux_stm32_config dmamux_stm32_config_##index = { \
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const struct dmamux_stm32_config dmamux_stm32_config_##index = { \
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.pclken = { .bus = DT_INST_CLOCKS_CELL(index, bus), \
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DMAMUX_CLOCK_INIT(index) \
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.enr = DT_INST_CLOCKS_CELL(index, bits) }, \
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.base = DT_INST_REG_ADDR(index), \
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.base = DT_INST_REG_ADDR(index), \
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.channel_nb = DT_INST_PROP(index, dma_channels), \
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.channel_nb = DT_INST_PROP(index, dma_channels), \
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.gen_nb = DT_INST_PROP(index, dma_generators), \
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.gen_nb = DT_INST_PROP(index, dma_generators), \
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@ -13,23 +13,6 @@ struct dmamux_stm32_channel {
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uint8_t dma_id; /* ref of the associated dma stream for this instance */
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uint8_t dma_id; /* ref of the associated dma stream for this instance */
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};
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};
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/* the table of all the dmamux channel */
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struct dmamux_stm32_data {
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void *callback_arg;
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void (*dmamux_callback)(void *arg, uint32_t id,
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int error_code);
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};
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/* this is the configuration of the dmamux IP */
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struct dmamux_stm32_config {
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struct stm32_pclken pclken;
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uint32_t base;
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uint8_t channel_nb; /* total nb of channels */
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uint8_t gen_nb; /* total nb of Request generator */
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uint8_t req_nb; /* total nb of Peripheral Request inputs */
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const struct dmamux_stm32_channel *mux_channels;
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};
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uint32_t table_ll_channel[] = {
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uint32_t table_ll_channel[] = {
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LL_DMAMUX_CHANNEL_0,
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LL_DMAMUX_CHANNEL_0,
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LL_DMAMUX_CHANNEL_1,
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LL_DMAMUX_CHANNEL_1,
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