soc: Add the MAX32662 SoC

Add MAX32662 Kconfig and dts files

Co-authored-by: Maureen Helm <maureen.helm@analog.com>
Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>

dts/arm/adi/max32/max32662-pinctrl.dtsi

@@ -0,0 +1,238 @@
+/*
+ * Copyright (c) 2024 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/max32-pinctrl.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller@40008000 {
+
+			/omit-if-no-ref/ swdio_p0_0: swdio_p0_0 {
+				pinmux = <MAX32_PINMUX(0, 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ pt0b_p0_0: pt0b_p0_0 {
+				pinmux = <MAX32_PINMUX(0, 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr0c_oa_p0_0: tmr0c_oa_p0_0 {
+				pinmux = <MAX32_PINMUX(0, 0, AF3)>;
+			};
+
+			/omit-if-no-ref/ tmr1d_oa_p0_0: tmr1d_oa_p0_0 {
+				pinmux = <MAX32_PINMUX(0, 0, AF4)>;
+			};
+
+			/omit-if-no-ref/ adc_trig_e_p0_0: adc_trig_e_p0_0 {
+				pinmux = <MAX32_PINMUX(0, 0, AF5)>;
+			};
+
+			/omit-if-no-ref/ swdclk_p0_1: swdclk_p0_1 {
+				pinmux = <MAX32_PINMUX(0, 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ pt1b_p0_1: pt1b_p0_1 {
+				pinmux = <MAX32_PINMUX(0, 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr0c_ia_p0_1: tmr0c_ia_p0_1 {
+				pinmux = <MAX32_PINMUX(0, 1, AF3)>;
+			};
+
+			/omit-if-no-ref/ tmr1d_ia_p0_1: tmr1d_ia_p0_1 {
+				pinmux = <MAX32_PINMUX(0, 1, AF4)>;
+			};
+
+			/omit-if-no-ref/ spi0a_cito_p0_2: spi0a_cito_p0_2 {
+				pinmux = <MAX32_PINMUX(0, 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart1b_tx_p0_2: uart1b_tx_p0_2 {
+				pinmux = <MAX32_PINMUX(0, 2, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr0c_ia_p0_2: tmr0c_ia_p0_2 {
+				pinmux = <MAX32_PINMUX(0, 2, AF3)>;
+			};
+
+			/omit-if-no-ref/ pt0d_p0_2: pt0d_p0_2 {
+				pinmux = <MAX32_PINMUX(0, 2, AF4)>;
+			};
+
+			/omit-if-no-ref/ i2s0e_sdo_p0_2: i2s0e_sdo_p0_2 {
+				pinmux = <MAX32_PINMUX(0, 2, AF5)>;
+			};
+
+			/omit-if-no-ref/ spi0a_copi_p0_3: spi0a_copi_p0_3 {
+				pinmux = <MAX32_PINMUX(0, 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart1b_rx_p0_3: uart1b_rx_p0_3 {
+				pinmux = <MAX32_PINMUX(0, 3, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr0c_oa_p0_3: tmr0c_oa_p0_3 {
+				pinmux = <MAX32_PINMUX(0, 3, AF3)>;
+			};
+
+			/omit-if-no-ref/ pt1d_p0_3: pt1d_p0_3 {
+				pinmux = <MAX32_PINMUX(0, 3, AF4)>;
+			};
+
+			/omit-if-no-ref/ i2s0e_sdi_p0_3: i2s0e_sdi_p0_3 {
+				pinmux = <MAX32_PINMUX(0, 3, AF5)>;
+			};
+
+			/omit-if-no-ref/ spi0a_sck_p0_4: spi0a_sck_p0_4 {
+				pinmux = <MAX32_PINMUX(0, 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart1b_cts_p0_4: uart1b_cts_p0_4 {
+				pinmux = <MAX32_PINMUX(0, 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr1c_ia_p0_4: tmr1c_ia_p0_4 {
+				pinmux = <MAX32_PINMUX(0, 4, AF3)>;
+			};
+
+			/omit-if-no-ref/ pt2d_p0_4: pt2d_p0_4 {
+				pinmux = <MAX32_PINMUX(0, 4, AF4)>;
+			};
+
+			/omit-if-no-ref/ i2s0e_bclk_p0_4: i2s0e_bclk_p0_4 {
+				pinmux = <MAX32_PINMUX(0, 4, AF5)>;
+			};
+
+			/omit-if-no-ref/ spi0a_ts0_p0_5: spi0a_ts0_p0_5 {
+				pinmux = <MAX32_PINMUX(0, 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart1b_rts_p0_5: uart1b_rts_p0_5 {
+				pinmux = <MAX32_PINMUX(0, 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr1c_oa_p0_5: tmr1c_oa_p0_5 {
+				pinmux = <MAX32_PINMUX(0, 5, AF3)>;
+			};
+
+			/omit-if-no-ref/ pt3d_p0_5: pt3d_p0_5 {
+				pinmux = <MAX32_PINMUX(0, 5, AF4)>;
+			};
+
+			/omit-if-no-ref/ i2s0e_lrclk_p0_5: i2s0e_lrclk_p0_5 {
+				pinmux = <MAX32_PINMUX(0, 5, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2c1a_scl_p0_6: i2c1a_scl_p0_6 {
+				pinmux = <MAX32_PINMUX(0, 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ can0b_rx_p0_6: can0b_rx_p0_6 {
+				pinmux = <MAX32_PINMUX(0, 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr2c_ia_p0_6: tmr2c_ia_p0_6 {
+				pinmux = <MAX32_PINMUX(0, 6, AF3)>;
+			};
+
+			/omit-if-no-ref/ hf_ext_clk_p0_6: hf_ext_clk_p0_6 {
+				pinmux = <MAX32_PINMUX(0, 6, AF4)>;
+			};
+
+			/omit-if-no-ref/ pt2e_p0_6: pt2e_p0_6 {
+				pinmux = <MAX32_PINMUX(0, 6, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2c1a_sda_p0_9: i2c1a_sda_p0_9 {
+				pinmux = <MAX32_PINMUX(0, 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ can0b_tx_p0_9: can0b_tx_p0_9 {
+				pinmux = <MAX32_PINMUX(0, 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr2c_oa_p0_9: tmr2c_oa_p0_9 {
+				pinmux = <MAX32_PINMUX(0, 9, AF3)>;
+			};
+
+			/omit-if-no-ref/ adc_trig_d_p0_9: adc_trig_d_p0_9 {
+				pinmux = <MAX32_PINMUX(0, 9, AF4)>;
+			};
+
+			/omit-if-no-ref/ pt3e_p0_9: pt3e_p0_9 {
+				pinmux = <MAX32_PINMUX(0, 9, AF5)>;
+			};
+
+			/omit-if-no-ref/ uart0a_tx_p0_10: uart0a_tx_p0_10 {
+				pinmux = <MAX32_PINMUX(0, 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi1b_ts0_p0_10: spi1b_ts0_p0_10 {
+				pinmux = <MAX32_PINMUX(0, 10, AF2)>;
+			};
+
+			/omit-if-no-ref/ ain3_p0_10: ain3_p0_10 {
+				pinmux = <MAX32_PINMUX(0, 10, AF4)>;
+			};
+
+			/omit-if-no-ref/ uart0a_rx_p0_11: uart0a_rx_p0_11 {
+				pinmux = <MAX32_PINMUX(0, 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi1b_sck_p0_11: spi1b_sck_p0_11 {
+				pinmux = <MAX32_PINMUX(0, 11, AF2)>;
+			};
+
+			/omit-if-no-ref/ cal32k_p0_11: cal32k_p0_11 {
+				pinmux = <MAX32_PINMUX(0, 11, AF3)>;
+			};
+
+			/omit-if-no-ref/ ain2_p0_11: ain2_p0_11 {
+				pinmux = <MAX32_PINMUX(0, 11, AF4)>;
+			};
+
+			/omit-if-no-ref/ lp_ext_clk_p0_11: lp_ext_clk_p0_11 {
+				pinmux = <MAX32_PINMUX(0, 11, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2c0a_scl_p0_12: i2c0a_scl_p0_12 {
+				pinmux = <MAX32_PINMUX(0, 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi1b_coti_p0_12: spi1b_coti_p0_12 {
+				pinmux = <MAX32_PINMUX(0, 12, AF2)>;
+			};
+
+			/omit-if-no-ref/ lptmr0c_ia_p0_12: lptmr0c_ia_p0_12 {
+				pinmux = <MAX32_PINMUX(0, 12, AF3)>;
+			};
+
+			/omit-if-no-ref/ ain1_p0_12: ain1_p0_12 {
+				pinmux = <MAX32_PINMUX(0, 12, AF4)>;
+			};
+
+			/omit-if-no-ref/ lptmr0e_oan_p0_12: lptmr0e_oan_p0_12 {
+				pinmux = <MAX32_PINMUX(0, 12, AF5)>;
+			};
+
+			/omit-if-no-ref/ i2c0a_sda_p0_13: i2c0a_sda_p0_13 {
+				pinmux = <MAX32_PINMUX(0, 13, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi1b_cito_p0_13: spi1b_cito_p0_13 {
+				pinmux = <MAX32_PINMUX(0, 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ lptmr0c_oa_p0_13: lptmr0c_oa_p0_13 {
+				pinmux = <MAX32_PINMUX(0, 13, AF3)>;
+			};
+
+			/omit-if-no-ref/ ain0_p0_13: ain0_p0_13 {
+				pinmux = <MAX32_PINMUX(0, 13, AF4)>;
+			};
+		};
+	};
+};

dts/arm/adi/max32/max32662.dtsi

@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2024 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv7-m.dtsi>
+#include <adi/max32/max32xxx.dtsi>
+
+&flash0 {
+	reg = <0x10000000 DT_SIZE_K(256)>;
+};
+
+&sram0 {
+	reg = <0x20000000 DT_SIZE_K(16)>;
+};
+
+/delete-node/ &clk_iso;
+
+/delete-node/ &gpio1;
+
+/delete-node/ &uart2;
+
+/* MAX32662 extra peripherals. */
+/ {
+	soc {
+		sram1: memory@20004000 {
+			compatible = "mmio-sram";
+			reg = <0x20004000 DT_SIZE_K(16)>;
+		};
+
+		sram2: memory@20008000 {
+			compatible = "mmio-sram";
+			reg = <0x20008000 DT_SIZE_K(16)>;
+		};
+
+		sram3: memory@2000c000 {
+			compatible = "mmio-sram";
+			reg = <0x2000c000 DT_SIZE_K(16)>;
+		};
+
+		sram4: memory@20010000 {
+			compatible = "mmio-sram";
+			reg = <0x20010000 DT_SIZE_K(4)>;
+		};
+
+		sram5: memory@20011000 {
+			compatible = "mmio-sram";
+			reg = <0x20011000 DT_SIZE_K(4)>;
+		};
+
+		sram6: memory@20012000 {
+			compatible = "mmio-sram";
+			reg = <0x20012000 DT_SIZE_K(4)>;
+		};
+
+		sram7: memory@20013000 {
+			compatible = "mmio-sram";
+			reg = <0x20013000 DT_SIZE_K(4)>;
+		};
+	};
+};

soc/adi/max32/Kconfig

@@ -14,6 +14,9 @@ config SOC_FAMILY_MAX32
 config SOC_MAX32655
 	select CPU_CORTEX_M4
 
+config SOC_MAX32662
+	select CPU_CORTEX_M4
+
 config SOC_MAX32670
 	select CPU_CORTEX_M4
 

soc/adi/max32/Kconfig.defconfig.max32662

@@ -0,0 +1,14 @@
+# Analog Devices MAX32662 MCU
+
+# Copyright (c) 2024 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_MAX32662
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/clocks/clk_ipo,clock-frequency)
+
+config NUM_IRQS
+	default 108
+
+endif # SOC_MAX32662

soc/adi/max32/Kconfig.soc

@@ -17,6 +17,10 @@ config SOC_MAX32655_M4
 	bool
 	select SOC_MAX32655
 
+config SOC_MAX32662
+	bool
+	select SOC_FAMILY_MAX32
+
 config SOC_MAX32670
 	bool
 	select SOC_FAMILY_MAX32
@@ -47,6 +51,7 @@ config SOC_MAX32690_M4
 
 config SOC
 	default "max32655" if SOC_MAX32655
+	default "max32662" if SOC_MAX32662
 	default "max32670" if SOC_MAX32670
 	default "max32672" if SOC_MAX32672
 	default "max32675" if SOC_MAX32675

soc/adi/max32/soc.yml

@@ -7,6 +7,7 @@ family:
   - name: max32655
     cpuclusters:
     - name: m4
+  - name: max32662
   - name: max32670
   - name: max32672
   - name: max32675