diff --git a/drivers/mm/CMakeLists.txt b/drivers/mm/CMakeLists.txt
index 00b3b6c0d81..36c8a414070 100644
--- a/drivers/mm/CMakeLists.txt
+++ b/drivers/mm/CMakeLists.txt
@@ -12,5 +12,6 @@ zephyr_library_sources_ifdef(
 
 zephyr_sources_ifdef(
 	CONFIG_MM_DRV_INTEL_ADSP_MTL_TLB
+	mm_drv_intel_adsp_regions.c
 	mm_drv_intel_adsp_mtl_tlb.c
 	)
diff --git a/drivers/mm/mm_drv_intel_adsp.h b/drivers/mm/mm_drv_intel_adsp.h
index 705263c7940..b62e7ceb27d 100644
--- a/drivers/mm/mm_drv_intel_adsp.h
+++ b/drivers/mm/mm_drv_intel_adsp.h
@@ -26,6 +26,7 @@
 
 #include <soc.h>
 #include <adsp_memory.h>
+#include <adsp_memory_regions.h>
 
 #include "mm_drv_common.h"
 
@@ -59,9 +60,6 @@ DEVICE_MMIO_TOPLEVEL_STATIC(tlb_regs, DT_DRV_INST(0));
 #define L2_SRAM_BANK_NUM			(L2_SRAM_SIZE / SRAM_BANK_SIZE)
 #define IS_BIT_SET(value, idx)		((value) & (1 << (idx)))
 
-/* size of TLB table */
-#define TLB_SIZE DT_REG_SIZE_BY_IDX(DT_INST(0, intel_adsp_mtl_tlb), 0)
-
 /**
  * Calculate TLB entry based on physical address.
  *
@@ -85,4 +83,13 @@ static inline uintptr_t tlb_entry_to_pa(uint16_t tlb_entry)
 		CONFIG_MM_DRV_PAGE_SIZE) + TLB_PHYS_BASE);
 }
 
+/**
+ * Calculate virtual memory regions allocation based on
+ * info from linker script.
+ *
+ * @param End address of staticaly allocated memory.
+ * @return Error Code.
+ */
+int calculate_memory_regions(uintptr_t static_alloc_end_ptr);
+
 #endif /* ZEPHYR_DRIVERS_SYSTEM_MM_DRV_INTEL_MTL_ */
diff --git a/drivers/mm/mm_drv_intel_adsp_mtl_tlb.c b/drivers/mm/mm_drv_intel_adsp_mtl_tlb.c
index 3160fc30e29..2e052921a84 100644
--- a/drivers/mm/mm_drv_intel_adsp_mtl_tlb.c
+++ b/drivers/mm/mm_drv_intel_adsp_mtl_tlb.c
@@ -589,6 +589,10 @@ static int sys_mm_drv_mm_init(const struct device *dev)
 
 	L2_PHYS_SRAM_REGION.num_blocks = avalible_memory_size / CONFIG_MM_DRV_PAGE_SIZE;
 
+	ret = calculate_memory_regions(UNUSED_L2_START_ALIGNED);
+	CHECKIF(ret != 0) {
+		return ret;
+	}
 	/*
 	 * Initialize memblocks that will store physical
 	 * page usage. Initially all physical pages are
@@ -619,6 +623,7 @@ static int sys_mm_drv_mm_init(const struct device *dev)
 	 */
 	if (L2_SRAM_BASE + L2_SRAM_SIZE < UNUSED_L2_START_ALIGNED ||
 	    L2_SRAM_BASE > UNUSED_L2_START_ALIGNED) {
+
 		__ASSERT(false,
 			 "unused l2 pointer is outside of l2 sram range %p\n",
 			 UNUSED_L2_START_ALIGNED);
diff --git a/drivers/mm/mm_drv_intel_adsp_regions.c b/drivers/mm/mm_drv_intel_adsp_regions.c
new file mode 100644
index 00000000000..571dfbb19bf
--- /dev/null
+++ b/drivers/mm/mm_drv_intel_adsp_regions.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2022 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Driver handling memory regions related
+ * functions
+ */
+
+#include "mm_drv_intel_adsp.h"
+
+struct sys_mm_drv_region
+virtual_memory_regions[CONFIG_MP_MAX_NUM_CPUS + VIRTUAL_REGION_COUNT] = { {0} };
+
+const struct sys_mm_drv_region *sys_mm_drv_query_memory_regions(void)
+{
+	return (const struct sys_mm_drv_region *) virtual_memory_regions;
+}
+
+static inline void append_region(void *address, uint32_t mem_size,
+	uint32_t attributes, uint32_t position, uint32_t *checksum)
+{
+	virtual_memory_regions[position].addr = address;
+	virtual_memory_regions[position].size = mem_size;
+	virtual_memory_regions[position].attr = attributes;
+	checksum += mem_size;
+}
+
+int calculate_memory_regions(uintptr_t static_alloc_end_ptr)
+{
+	struct sys_mm_drv_region *temporary_table =
+		(struct sys_mm_drv_region *)&virtual_memory_regions[0];
+
+	int i, checksum = 0;
+
+	for (i = 0; i < CONFIG_MP_MAX_NUM_CPUS; i++)	{
+		append_region((void *)(static_alloc_end_ptr + i * CORE_HEAP_SIZE),
+			CORE_HEAP_SIZE, MEM_REG_ATTR_CORE_HEAP, i, &checksum);
+	}
+
+	append_region((void *)((uintptr_t)
+		virtual_memory_regions[i - 1].addr + temporary_table[i - 1].size),
+		CORE_HEAP_SIZE, MEM_REG_ATTR_SHARED_HEAP, i, &checksum);
+	i++;
+	append_region((void *)((uintptr_t)
+		virtual_memory_regions[i - 1].addr + temporary_table[i - 1].size),
+		OPPORTUNISTIC_REGION_SIZE, MEM_REG_ATTR_OPPORTUNISTIC_MEMORY, i, &checksum);
+	i++;
+	/* Apending last region as 0 so iterators know where table is over
+	 * check is for size = 0;
+	 */
+	append_region((void *)0, 0, 0, i, &checksum);
+
+	if (checksum > L2_VIRTUAL_SRAM_SIZE) {
+		return -EINVAL;
+	}
+
+	return 0;
+}
diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_memory_regions.h b/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_memory_regions.h
new file mode 100644
index 00000000000..e235014f76a
--- /dev/null
+++ b/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_memory_regions.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2022 Intel Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_INTEL_ADSP_MEMORY_REGIONS_H_
+#define ZEPHYR_SOC_INTEL_ADSP_MEMORY_REGIONS_H_
+
+/* Define amount of regions other than core heaps that virtual memory will be split to
+ * currently includes shared heap and oma region and one regions set to 0 as for table
+ * iterator end value.
+ */
+#define VIRTUAL_REGION_COUNT 3
+
+#define CORE_HEAP_SIZE 0x100000
+#define SHARED_HEAP_SIZE 0x100000
+#define OPPORTUNISTIC_REGION_SIZE 0x100000
+
+/* size of TLB table */
+#define TLB_SIZE DT_REG_SIZE_BY_IDX(DT_INST(0, intel_adsp_mtl_tlb), 0)
+
+/* Attribiutes for memory regions */
+#define MEM_REG_ATTR_CORE_HEAP 1U
+#define MEM_REG_ATTR_SHARED_HEAP 2U
+#define MEM_REG_ATTR_OPPORTUNISTIC_MEMORY 4U
+
+#endif /* ZEPHYR_SOC_INTEL_ADSP_MEMORY_REGIONS_H_ */