From 72e6955f304e73b92ddaedba4f78adcf67c14655 Mon Sep 17 00:00:00 2001 From: Mathieu CHOPLAIN Date: Mon, 9 Jun 2025 09:41:20 +0200 Subject: [PATCH] boards: stm32: stm32n6570_dk: fix DTS errors for Ethernet The DTS for this board contained a few mistakes: * The PHY address was incorrect * This did not impair functionality because the RTL8211F treats address 0 as "broadcast" and accepts commands sent to it by default * An incorrect PHY driver was used * The generic "phy_mii" driver is not the most appropriate for this PHY - use the HW-specific RTL8211F driver instead * Also remove the PHY IRQ pin configuration from Ethernet pinctrl to allow RTL8211F driver to receive IRQ via GPIO instead * The RGMII GTX CLK pinctrl must be configured at "medium-speed" * This is a temporary solution. The proper solution would use very-high-speed combined with a GPIO delay, but delays are not supported yet in Zephyr. Signed-off-by: Mathieu CHOPLAIN --- .../stm32n6570_dk/stm32n6570_dk_common.dtsi | 29 +++++++++++++++---- 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/boards/st/stm32n6570_dk/stm32n6570_dk_common.dtsi b/boards/st/stm32n6570_dk/stm32n6570_dk_common.dtsi index 8b643d45ba9..6eddc4fca8b 100644 --- a/boards/st/stm32n6570_dk/stm32n6570_dk_common.dtsi +++ b/boards/st/stm32n6570_dk/stm32n6570_dk_common.dtsi @@ -344,6 +344,15 @@ zephyr_udc0: &usbotg_hs1 { }; }; +/** + * Board-specific configuration, required to ensure that + * the Tx CLK and DAT signals arrive in sync at the PHY. + * Without this, the Tx will be unreliable + */ +ð1_rgmii_gtx_clk_pf0 { + slew-rate = "medium-speed"; +}; + &mac { status = "okay"; pinctrl-0 = <ð1_rgmii_gtx_clk_pf0 @@ -358,8 +367,7 @@ zephyr_udc0: &usbotg_hs1 { ð1_rgmii_rxd0_pf14 ð1_rgmii_rxd1_pf15 ð1_rgmii_txd2_pg3 - ð1_rgmii_txd3_pg4 - ð1_phy_intn_pd3>; + ð1_rgmii_txd3_pg4>; pinctrl-names = "default"; phy-connection-type = "rgmii"; phy-handle = <ð_phy>; @@ -370,9 +378,20 @@ zephyr_udc0: &usbotg_hs1 { pinctrl-0 = <ð1_mdio_pd12 ð1_mdc_pd1>; pinctrl-names = "default"; - eth_phy: ethernet-phy@0 { - compatible = "ethernet-phy"; - reg = <0x0>; + eth_phy: ethernet-phy@1 { + compatible = "realtek,rtl8211f"; + reg = <0x1>; + /** + * PD3 can be used as alternate function ETH1_PHY_INTN, + * which allows the Ethernet MAC to sense interrupts from + * the PHY in order to signal them to the CPU via its own + * interrupt lines. However, the Zephyr RTL8211F driver + * is unaware of this mechanism. Skip configuring PD3 as + * alternate function (in pinctrl of &mac) and provide the + * pin to the RTL8211F driver for interrupt sensing using + * the regular GPIO interrupt APIs. + */ + int-gpios = <&gpiod 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; }; };