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intel_adsp: rename clock registers due to possible conflict

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SOF using the same defines and in some cases generating conflicts.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2022-07-27 09:12:29 -04:00
commit 728d8eb2c0
6 changed files with 36 additions and 36 deletions
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12
drivers/timer/intel_adsp_timer.c
View file

@ -42,11 +42,11 @@
BUILD_ASSERT(MIN_DELAY < CYC_PER_TICK); BUILD_ASSERT(MIN_DELAY < CYC_PER_TICK);
BUILD_ASSERT(COMPARATOR_IDX >= 0 && COMPARATOR_IDX <= 1); BUILD_ASSERT(COMPARATOR_IDX >= 0 && COMPARATOR_IDX <= 1);
#define WCTCS (SHIM_DSPWCTS) #define WCTCS (ADSP_SHIM_DSPWCTS)
#define COUNTER_HI (SHIM_DSPWCH) #define COUNTER_HI (ADSP_SHIM_DSPWCH)
#define COUNTER_LO (SHIM_DSPWCL) #define COUNTER_LO (ADSP_SHIM_DSPWCL)
#define COMPARE_HI (SHIM_COMPARE_HI(COMPARATOR_IDX)) #define COMPARE_HI (ADSP_SHIM_COMPARE_HI(COMPARATOR_IDX))
#define COMPARE_LO (SHIM_COMPARE_LO(COMPARATOR_IDX)) #define COMPARE_LO (ADSP_SHIM_COMPARE_LO(COMPARATOR_IDX))
static struct k_spinlock lock; static struct k_spinlock lock;
@ -191,7 +191,7 @@ static void irq_init(void)
*/ */
#ifdef CONFIG_SOC_SERIES_INTEL_ACE1X #ifdef CONFIG_SOC_SERIES_INTEL_ACE1X
MTL_DINT[cpu].ie[MTL_INTL_TTS] |= BIT(COMPARATOR_IDX + 1); MTL_DINT[cpu].ie[MTL_INTL_TTS] |= BIT(COMPARATOR_IDX + 1);
*WCTCS |= SHIM_DSPWCTCS_TTIE(COMPARATOR_IDX); *WCTCS |= ADSP_SHIM_DSPWCTCS_TTIE(COMPARATOR_IDX);
#else #else
CAVS_INTCTRL[cpu].l2.clear = CAVS_L2_DWCT0; CAVS_INTCTRL[cpu].l2.clear = CAVS_L2_DWCT0;
#endif #endif

12
soc/xtensa/intel_adsp/ace_v1x/ace_v1x-regs.h
View file

@ -70,13 +70,13 @@ struct mtl_tts {
#define MTL_TTS (*(volatile struct mtl_tts *)DFTTS_REG) #define MTL_TTS (*(volatile struct mtl_tts *)DFTTS_REG)
#define SHIM_DSPWCTS (&MTL_TTS.wctcs) #define ADSP_SHIM_DSPWCTS (&MTL_TTS.wctcs)
#define SHIM_DSPWCH (&MTL_TTS.wc.hi) #define ADSP_SHIM_DSPWCH (&MTL_TTS.wc.hi)
#define SHIM_DSPWCL (&MTL_TTS.wc.lo) #define ADSP_SHIM_DSPWCL (&MTL_TTS.wc.lo)
#define SHIM_COMPARE_HI(idx) (&MTL_TTS.wctc[idx].hi) #define ADSP_SHIM_COMPARE_HI(idx) (&MTL_TTS.wctc[idx].hi)
#define SHIM_COMPARE_LO(idx) (&MTL_TTS.wctc[idx].lo) #define ADSP_SHIM_COMPARE_LO(idx) (&MTL_TTS.wctc[idx].lo)
#define SHIM_DSPWCTCS_TTIE(c) BIT(8 + (c)) #define ADSP_SHIM_DSPWCTCS_TTIE(c) BIT(8 + (c))
/* Low priority interrupt indices */ /* Low priority interrupt indices */
#define MTL_INTL_HIPC 0 #define MTL_INTL_HIPC 0

12
soc/xtensa/intel_adsp/cavs/include/intel_apl_adsp/adsp_shim.h
View file

@ -67,13 +67,13 @@ struct cavs_shim {
#define CAVS_SHIM (*((volatile struct cavs_shim *)DT_REG_ADDR(DT_NODELABEL(shim)))) #define CAVS_SHIM (*((volatile struct cavs_shim *)DT_REG_ADDR(DT_NODELABEL(shim))))
#define SHIM_DSPWCTS (&CAVS_SHIM.dspwctcs) #define ADSP_SHIM_DSPWCTS (&CAVS_SHIM.dspwctcs)
#define SHIM_DSPWCH (&CAVS_SHIM.dspwc_hi) #define ADSP_SHIM_DSPWCH (&CAVS_SHIM.dspwc_hi)
#define SHIM_DSPWCL (&CAVS_SHIM.dspwc_lo) #define ADSP_SHIM_DSPWCL (&CAVS_SHIM.dspwc_lo)
#define SHIM_COMPARE_HI(idx) (&CAVS_SHIM.UTIL_CAT(UTIL_CAT(dspwct, idx), c_hi)) #define ADSP_SHIM_COMPARE_HI(idx) (&CAVS_SHIM.UTIL_CAT(UTIL_CAT(dspwct, idx), c_hi))
#define SHIM_COMPARE_LO(idx) (&CAVS_SHIM.UTIL_CAT(UTIL_CAT(dspwct, idx), c_lo)) #define ADSP_SHIM_COMPARE_LO(idx) (&CAVS_SHIM.UTIL_CAT(UTIL_CAT(dspwct, idx), c_lo))
#define SHIM_DSPWCTCS_TTIE(c) BIT(8 + (c)) #define ADSP_SHIM_DSPWCTCS_TTIE(c) BIT(8 + (c))
/* L2 Local Memory control (cAVS 1.8+) */ /* L2 Local Memory control (cAVS 1.8+) */
struct cavs_l2lm { struct cavs_l2lm {

12
soc/xtensa/intel_adsp/cavs/include/intel_cnl_adsp/adsp_shim.h
View file

@ -67,13 +67,13 @@ struct cavs_shim {
#define CAVS_SHIM (*((volatile struct cavs_shim *)DT_REG_ADDR(DT_NODELABEL(shim)))) #define CAVS_SHIM (*((volatile struct cavs_shim *)DT_REG_ADDR(DT_NODELABEL(shim))))
#define SHIM_DSPWCTS (&CAVS_SHIM.dspwctcs) #define ADSP_SHIM_DSPWCTS (&CAVS_SHIM.dspwctcs)
#define SHIM_DSPWCH (&CAVS_SHIM.dspwc_hi) #define ADSP_SHIM_DSPWCH (&CAVS_SHIM.dspwc_hi)
#define SHIM_DSPWCL (&CAVS_SHIM.dspwc_lo) #define ADSP_SHIM_DSPWCL (&CAVS_SHIM.dspwc_lo)
#define SHIM_COMPARE_HI(idx) (&CAVS_SHIM.UTIL_CAT(UTIL_CAT(dspwct, idx), c_hi)) #define ADSP_SHIM_COMPARE_HI(idx) (&CAVS_SHIM.UTIL_CAT(UTIL_CAT(dspwct, idx), c_hi))
#define SHIM_COMPARE_LO(idx) (&CAVS_SHIM.UTIL_CAT(UTIL_CAT(dspwct, idx), c_lo)) #define ADSP_SHIM_COMPARE_LO(idx) (&CAVS_SHIM.UTIL_CAT(UTIL_CAT(dspwct, idx), c_lo))
#define SHIM_DSPWCTCS_TTIE(c) BIT(8 + (c)) #define ADSP_SHIM_DSPWCTCS_TTIE(c) BIT(8 + (c))
/* L2 Local Memory control (cAVS 1.8+) */ /* L2 Local Memory control (cAVS 1.8+) */
struct cavs_l2lm { struct cavs_l2lm {

12
soc/xtensa/intel_adsp/cavs/include/intel_icl_adsp/adsp_shim.h
View file

@ -67,13 +67,13 @@ struct cavs_shim {
#define CAVS_SHIM (*((volatile struct cavs_shim *)DT_REG_ADDR(DT_NODELABEL(shim)))) #define CAVS_SHIM (*((volatile struct cavs_shim *)DT_REG_ADDR(DT_NODELABEL(shim))))
#define SHIM_DSPWCTS (&CAVS_SHIM.dspwctcs) #define ADSP_SHIM_DSPWCTS (&CAVS_SHIM.dspwctcs)
#define SHIM_DSPWCH (&CAVS_SHIM.dspwc_hi) #define ADSP_SHIM_DSPWCH (&CAVS_SHIM.dspwc_hi)
#define SHIM_DSPWCL (&CAVS_SHIM.dspwc_lo) #define ADSP_SHIM_DSPWCL (&CAVS_SHIM.dspwc_lo)
#define SHIM_COMPARE_HI(idx) (&CAVS_SHIM.UTIL_CAT(UTIL_CAT(dspwct, idx), c_hi)) #define ADSP_SHIM_COMPARE_HI(idx) (&CAVS_SHIM.UTIL_CAT(UTIL_CAT(dspwct, idx), c_hi))
#define SHIM_COMPARE_LO(idx) (&CAVS_SHIM.UTIL_CAT(UTIL_CAT(dspwct, idx), c_lo)) #define ADSP_SHIM_COMPARE_LO(idx) (&CAVS_SHIM.UTIL_CAT(UTIL_CAT(dspwct, idx), c_lo))
#define SHIM_DSPWCTCS_TTIE(c) BIT(8 + (c)) #define ADSP_SHIM_DSPWCTCS_TTIE(c) BIT(8 + (c))
/* L2 Local Memory control (cAVS 1.8+) */ /* L2 Local Memory control (cAVS 1.8+) */
struct cavs_l2lm { struct cavs_l2lm {

12
soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/adsp_shim.h
View file

@ -67,13 +67,13 @@ struct cavs_shim {
#define CAVS_SHIM (*((volatile struct cavs_shim *)DT_REG_ADDR(DT_NODELABEL(shim)))) #define CAVS_SHIM (*((volatile struct cavs_shim *)DT_REG_ADDR(DT_NODELABEL(shim))))
#define SHIM_DSPWCTS (&CAVS_SHIM.dspwctcs) #define ADSP_SHIM_DSPWCTS (&CAVS_SHIM.dspwctcs)
#define SHIM_DSPWCH (&CAVS_SHIM.dspwc_hi) #define ADSP_SHIM_DSPWCH (&CAVS_SHIM.dspwc_hi)
#define SHIM_DSPWCL (&CAVS_SHIM.dspwc_lo) #define ADSP_SHIM_DSPWCL (&CAVS_SHIM.dspwc_lo)
#define SHIM_COMPARE_HI(idx) (&CAVS_SHIM.UTIL_CAT(UTIL_CAT(dspwct, idx), c_hi)) #define ADSP_SHIM_COMPARE_HI(idx) (&CAVS_SHIM.UTIL_CAT(UTIL_CAT(dspwct, idx), c_hi))
#define SHIM_COMPARE_LO(idx) (&CAVS_SHIM.UTIL_CAT(UTIL_CAT(dspwct, idx), c_lo)) #define ADSP_SHIM_COMPARE_LO(idx) (&CAVS_SHIM.UTIL_CAT(UTIL_CAT(dspwct, idx), c_lo))
#define SHIM_DSPWCTCS_TTIE(c) BIT(8 + (c)) #define ADSP_SHIM_DSPWCTCS_TTIE(c) BIT(8 + (c))
/* L2 Local Memory control (cAVS 1.8+) */ /* L2 Local Memory control (cAVS 1.8+) */
struct cavs_l2lm { struct cavs_l2lm {