drivers: interrupt_controller: Add XMC4XXX ERU driver
In Infineon XMC4XXX SoCs, gpio interrupts are triggered via an Event Request Unit (ERU) module. A subset of the gpios are connected to the ERU. The ERU monitors edge triggers and creates a SR. This driver configures the ERU for a target port/pin combination for rising/falling edge events. Note that the ERU module does not generate SR based on the gpio level. Internally the ERU tracks the *status* of an event. The status is set on a positive edge and unset on a negative edge (or vice-versa depending on the configuration). The value of the status is used to implement a level triggered interrupt; The ISR checks the status flag and calls the callback function if the status is set. The ERU configurations for supported port/pin combinations are stored in a devicetree file dts/arm/infineon/xmc4xxx_x_x-intc.dtsi. The configurations are stored in the opaque array uint16 port_line_mapping[]. Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
This commit is contained in:
Andriy Gelman
Carles Cufí
parent
a8a72c581e
commit
727e589448
12 changed files with 400 additions and 0 deletions
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@ -9,6 +9,7 @@
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/dts-v1/;
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/dts-v1/;
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#include <infineon/xmc4500_F100x1024.dtsi>
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#include <infineon/xmc4500_F100x1024.dtsi>
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#include <infineon/xmc4500_F100x1024-intc.dtsi>
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#include "xmc45_relax_kit-pinctrl.dtsi"
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#include "xmc45_relax_kit-pinctrl.dtsi"
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/ {
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/ {
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@ -31,6 +31,7 @@ zephyr_library_sources_ifdef(CONFIG_SWERV_PIC intc_swerv_pic.c)
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zephyr_library_sources_ifdef(CONFIG_VEXRISCV_LITEX_IRQ intc_vexriscv_litex.c)
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zephyr_library_sources_ifdef(CONFIG_VEXRISCV_LITEX_IRQ intc_vexriscv_litex.c)
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zephyr_library_sources_ifdef(CONFIG_NUCLEI_ECLIC intc_nuclei_eclic.c)
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zephyr_library_sources_ifdef(CONFIG_NUCLEI_ECLIC intc_nuclei_eclic.c)
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zephyr_library_sources_ifdef(CONFIG_NXP_S32_EIRQ intc_eirq_nxp_s32.c)
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zephyr_library_sources_ifdef(CONFIG_NXP_S32_EIRQ intc_eirq_nxp_s32.c)
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zephyr_library_sources_ifdef(CONFIG_XMC4XXX_INTC intc_xmc4xxx.c)
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if(CONFIG_INTEL_VTD_ICTL)
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if(CONFIG_INTEL_VTD_ICTL)
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zephyr_library_include_directories(${ZEPHYR_BASE}/arch/x86/include)
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zephyr_library_include_directories(${ZEPHYR_BASE}/arch/x86/include)
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@ -83,4 +83,6 @@ source "drivers/interrupt_controller/Kconfig.plic"
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source "drivers/interrupt_controller/Kconfig.nxp_s32"
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source "drivers/interrupt_controller/Kconfig.nxp_s32"
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source "drivers/interrupt_controller/Kconfig.xmc4xxx"
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endmenu
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endmenu
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12
drivers/interrupt_controller/Kconfig.xmc4xxx
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12
drivers/interrupt_controller/Kconfig.xmc4xxx
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@ -0,0 +1,12 @@
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# XMC4XXX INTC configuration
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# Copyright (c) Schlumberger
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# SPDX-License-Identifier: Apache-2.0
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config XMC4XXX_INTC
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bool "Interrupt Controller Driver for XMC4XXX series devices"
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default y
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depends on DT_HAS_INFINEON_XMC4XXX_INTC_ENABLED
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help
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Enable interrupt controller driver for XMC4XXX series of devices. This is required for
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GPIO interrupt support.
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227
drivers/interrupt_controller/intc_xmc4xxx.c
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227
drivers/interrupt_controller/intc_xmc4xxx.c
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/*
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* Copyright (c) 2022 Schlumberger
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT infineon_xmc4xxx_intc
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#include <zephyr/device.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/dt-bindings/interrupt-controller/infineon-xmc4xxx-intc.h>
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#include <zephyr/irq.h>
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#include <xmc_eru.h>
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/* In Infineon XMC4XXX SoCs, gpio interrupts are triggered via an Event Request Unit (ERU) */
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/* module. A subset of the GPIOs are connected to the ERU. The ERU monitors edge triggers */
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/* and creates a SR. */
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/* This driver configures the ERU for a target port/pin combination for rising/falling */
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/* edge events. Note that the ERU module does not generate SR based on the gpio level. */
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/* Internally the ERU tracks the *status* of an event. The status is set on a positive edge and */
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/* unset on a negative edge (or vice-versa depending on the configuration). The value of */
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/* the status is used to implement a level triggered interrupt; The ISR checks the status */
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/* flag and calls the callback function if the status is set. */
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/* The ERU configurations for supported port/pin combinations are stored in a devicetree file */
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/* dts/arm/infineon/xmc4xxx_x_x-intc.dtsi. The configurations are stored in the opaque array */
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/* uint16 port_line_mapping[]. The bitfields for the opaque entries are defined in */
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/* dt-bindings/interrupt-controller/infineon-xmc4xxx-intc.h. */
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struct isr_cb {
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/* if fn is NULL it implies the interrupt line has not been allocated */
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void (*fn)(const struct device *dev, int pin);
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void *data;
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enum gpio_int_mode mode;
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uint8_t port_id;
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uint8_t pin;
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};
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#define MAX_ISR_NUM 8
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struct intc_xmc4xxx_data {
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struct isr_cb cb[MAX_ISR_NUM];
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};
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#define NUM_ERUS 2
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struct intc_xmc4xxx_config {
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XMC_ERU_t *eru_regs[NUM_ERUS];
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};
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static const uint16_t port_line_mapping[DT_INST_PROP_LEN(0, port_line_mapping)] =
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DT_INST_PROP(0, port_line_mapping);
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int intc_xmc4xxx_gpio_enable_interrupt(int port_id, int pin, enum gpio_int_mode mode,
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enum gpio_int_trig trig,
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void (*fn)(const struct device *, int), void *user_data)
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{
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const struct device *dev = DEVICE_DT_INST_GET(0);
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struct intc_xmc4xxx_data *data = dev->data;
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const struct intc_xmc4xxx_config *config = dev->config;
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int ret = -ENOTSUP;
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for (int i = 0; i < ARRAY_SIZE(port_line_mapping); i++) {
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XMC_ERU_ETL_CONFIG_t etl_config = {0};
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XMC_ERU_OGU_CONFIG_t isr_config = {0};
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XMC_ERU_ETL_EDGE_DETECTION_t trig_xmc;
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XMC_ERU_t *eru;
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int port_map, pin_map, line, eru_src, eru_ch;
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struct isr_cb *cb;
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port_map = XMC4XXX_INTC_GET_PORT(port_line_mapping[i]);
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pin_map = XMC4XXX_INTC_GET_PIN(port_line_mapping[i]);
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if (port_map != port_id || pin_map != pin) {
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continue;
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}
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line = XMC4XXX_INTC_GET_LINE(port_line_mapping[i]);
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cb = &data->cb[line];
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if (cb->fn) {
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/* It's already used. Continue search for available line */
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/* with same port/pin */
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ret = -EBUSY;
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continue;
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}
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eru_src = XMC4XXX_INTC_GET_ERU_SRC(port_line_mapping[i]);
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eru_ch = line & 0x3;
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if (trig == GPIO_INT_TRIG_HIGH) {
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trig_xmc = XMC_ERU_ETL_EDGE_DETECTION_RISING;
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} else if (trig == GPIO_INT_TRIG_LOW) {
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trig_xmc = XMC_ERU_ETL_EDGE_DETECTION_FALLING;
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} else if (trig == GPIO_INT_TRIG_BOTH) {
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trig_xmc = XMC_ERU_ETL_EDGE_DETECTION_BOTH;
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} else {
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return -EINVAL;
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}
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cb->port_id = port_id;
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cb->pin = pin;
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cb->mode = mode;
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cb->fn = fn;
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cb->data = user_data;
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/* setup the eru */
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etl_config.edge_detection = trig_xmc;
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etl_config.input_a = eru_src;
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etl_config.input_b = eru_src;
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etl_config.source = eru_src >> 2;
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etl_config.status_flag_mode = XMC_ERU_ETL_STATUS_FLAG_MODE_HWCTRL;
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etl_config.enable_output_trigger = 1;
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etl_config.output_trigger_channel = eru_ch;
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eru = config->eru_regs[line >> 2];
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XMC_ERU_ETL_Init(eru, eru_ch, &etl_config);
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isr_config.service_request = XMC_ERU_OGU_SERVICE_REQUEST_ON_TRIGGER;
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XMC_ERU_OGU_Init(eru, eru_ch, &isr_config);
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/* if the gpio level is already set then we must manually set the interrupt to */
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/* pending */
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if (mode == GPIO_INT_MODE_LEVEL) {
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ret = gpio_pin_get_raw(user_data, pin);
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if (ret < 0) {
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return ret;
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}
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#define NVIC_ISPR_BASE 0xe000e200u
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if ((ret == 0 && trig == GPIO_INT_TRIG_LOW) ||
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(ret == 1 && trig == GPIO_INT_TRIG_HIGH)) {
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eru->EXICON_b[eru_ch].FL = 1;
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/* put interrupt into pending state */
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*(uint32_t *)(NVIC_ISPR_BASE) |= BIT(line + 1);
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}
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}
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return 0;
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}
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return ret;
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}
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int intc_xmc4xxx_gpio_disable_interrupt(int port_id, int pin)
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{
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const struct device *dev = DEVICE_DT_INST_GET(0);
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const struct intc_xmc4xxx_config *config = dev->config;
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struct intc_xmc4xxx_data *data = dev->data;
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int eru_ch;
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for (int line = 0; line < ARRAY_SIZE(data->cb); line++) {
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struct isr_cb *cb;
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cb = &data->cb[line];
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eru_ch = line & 0x3;
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if (cb->fn && cb->port_id == port_id && cb->pin == pin) {
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XMC_ERU_t *eru = config->eru_regs[line >> 2];
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cb->fn = NULL;
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/* disable the SR */
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eru->EXICON_b[eru_ch].PE = 0;
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/* unset the status flag */
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eru->EXICON_b[eru_ch].FL = 0;
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/* no need to clear other variables in cb*/
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return 0;
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}
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}
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return -EINVAL;
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}
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static void intc_xmc4xxx_isr(void *arg)
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{
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int line = (int)arg;
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const struct device *dev = DEVICE_DT_INST_GET(0);
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struct intc_xmc4xxx_data *data = dev->data;
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const struct intc_xmc4xxx_config *config = dev->config;
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struct isr_cb *cb = &data->cb[line];
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XMC_ERU_t *eru = config->eru_regs[line >> 2];
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int eru_ch = line & 0x3;
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/* The callback function may actually disable the interrupt and set cb->fn = NULL */
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/* as is done in tests/drivers/gpio/gpio_api_1pin. Assume that the callback function */
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/* will NOT disable the interrupt and then enable another port/pin */
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/* in the same callback which could potentially set cb->fn again. */
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while (cb->fn) {
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cb->fn(cb->data, cb->pin);
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/* for level triggered interrupts we have to manually check the status. */
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if (cb->mode == GPIO_INT_MODE_LEVEL && eru->EXICON_b[eru_ch].FL == 1) {
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continue;
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}
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/* break for edge triggered interrupts */
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break;
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}
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}
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#define INTC_IRQ_CONNECT_ENABLE(name, line_number) \
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COND_CODE_1(DT_INST_IRQ_HAS_NAME(0, name), \
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(IRQ_CONNECT(DT_INST_IRQ_BY_NAME(0, name, irq), \
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DT_INST_IRQ_BY_NAME(0, name, priority), intc_xmc4xxx_isr, (void *)line_number, 0); \
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irq_enable(DT_INST_IRQ_BY_NAME(0, name, irq));), ())
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static int intc_xmc4xxx_init(const struct device *dev)
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{
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/* connect irqs only if they defined by name in the dts */
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INTC_IRQ_CONNECT_ENABLE(eru0sr0, 0);
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INTC_IRQ_CONNECT_ENABLE(eru0sr1, 1);
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INTC_IRQ_CONNECT_ENABLE(eru0sr2, 2);
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INTC_IRQ_CONNECT_ENABLE(eru0sr3, 3);
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INTC_IRQ_CONNECT_ENABLE(eru1sr0, 4);
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INTC_IRQ_CONNECT_ENABLE(eru1sr1, 5);
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INTC_IRQ_CONNECT_ENABLE(eru1sr2, 6);
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INTC_IRQ_CONNECT_ENABLE(eru1sr3, 7);
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return 0;
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}
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struct intc_xmc4xxx_data intc_xmc4xxx_data0;
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struct intc_xmc4xxx_config intc_xmc4xxx_config0 = {
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.eru_regs = {
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(XMC_ERU_t *)DT_INST_REG_ADDR_BY_NAME(0, eru0),
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(XMC_ERU_t *)DT_INST_REG_ADDR_BY_NAME(0, eru1),
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},
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};
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DEVICE_DT_INST_DEFINE(0, intc_xmc4xxx_init, NULL,
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&intc_xmc4xxx_data0, &intc_xmc4xxx_config0, PRE_KERNEL_1,
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CONFIG_INTC_INIT_PRIORITY, NULL);
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44
dts/arm/infineon/xmc4500_F100x1024-intc.dtsi
Normal file
44
dts/arm/infineon/xmc4500_F100x1024-intc.dtsi
Normal file
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@ -0,0 +1,44 @@
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/*
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* Copyright (c) 2022 Schlumberger
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/interrupt-controller/infineon-xmc4xxx-intc.h>
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&intc {
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port-line-mapping = <
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XMC4XXX_INTC_SET_LINE_MAP(0, 1, 0, 0) /* ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 */
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XMC4XXX_INTC_SET_LINE_MAP(2, 5, 2, 0) /* ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 */
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XMC4XXX_INTC_SET_LINE_MAP(3, 2, 1, 0) /* ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 */
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XMC4XXX_INTC_SET_LINE_MAP(0, 0, 4, 0) /* ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 */
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XMC4XXX_INTC_SET_LINE_MAP(2, 0, 7, 0) /* ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 */
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XMC4XXX_INTC_SET_LINE_MAP(2, 4, 6, 0) /* ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 */
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XMC4XXX_INTC_SET_LINE_MAP(3, 1, 5, 0) /* ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 */
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XMC4XXX_INTC_SET_LINE_MAP(0, 10, 0, 1) /* ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 */
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XMC4XXX_INTC_SET_LINE_MAP(2, 3, 2, 1) /* ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 */
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XMC4XXX_INTC_SET_LINE_MAP(0, 9, 4, 1) /* ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 */
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XMC4XXX_INTC_SET_LINE_MAP(2, 2, 6, 1) /* ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 */
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XMC4XXX_INTC_SET_LINE_MAP(2, 6, 7, 1) /* ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 */
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XMC4XXX_INTC_SET_LINE_MAP(0, 8, 1, 2) /* ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 */
|
||||||
|
XMC4XXX_INTC_SET_LINE_MAP(1, 5, 0, 2) /* ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 */
|
||||||
|
XMC4XXX_INTC_SET_LINE_MAP(0, 12, 6, 2) /* ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 */
|
||||||
|
XMC4XXX_INTC_SET_LINE_MAP(0, 4, 7, 2) /* ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 */
|
||||||
|
XMC4XXX_INTC_SET_LINE_MAP(0, 7, 5, 2) /* ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 */
|
||||||
|
XMC4XXX_INTC_SET_LINE_MAP(1, 4, 4, 2) /* ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 */
|
||||||
|
XMC4XXX_INTC_SET_LINE_MAP(0, 11, 2, 3) /* ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 */
|
||||||
|
XMC4XXX_INTC_SET_LINE_MAP(1, 1, 0, 3) /* ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 */
|
||||||
|
XMC4XXX_INTC_SET_LINE_MAP(3, 6, 1, 3) /* ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 */
|
||||||
|
XMC4XXX_INTC_SET_LINE_MAP(0, 2, 7, 3) /* ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 */
|
||||||
|
XMC4XXX_INTC_SET_LINE_MAP(0, 6, 6, 3) /* ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 */
|
||||||
|
XMC4XXX_INTC_SET_LINE_MAP(1, 0, 4, 3) /* ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 */
|
||||||
|
XMC4XXX_INTC_SET_LINE_MAP(3, 5, 5, 3) /* ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 */
|
||||||
|
XMC4XXX_INTC_SET_LINE_MAP(1, 5, 0, 4) /* ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 */
|
||||||
|
XMC4XXX_INTC_SET_LINE_MAP(2, 1, 4, 4) /* ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 */
|
||||||
|
XMC4XXX_INTC_SET_LINE_MAP(1, 15, 0, 5) /* ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 */
|
||||||
|
XMC4XXX_INTC_SET_LINE_MAP(2, 7, 4, 5) /* ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 */
|
||||||
|
XMC4XXX_INTC_SET_LINE_MAP(1, 3, 0, 6) /* ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 */
|
||||||
|
XMC4XXX_INTC_SET_LINE_MAP(1, 2, 4, 6) /* ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 */
|
||||||
|
XMC4XXX_INTC_SET_LINE_MAP(0, 5, 0, 7) /* ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 */
|
||||||
|
XMC4XXX_INTC_SET_LINE_MAP(0, 3, 4, 7) /* ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 */
|
||||||
|
>;
|
||||||
|
};
|
||||||
|
|
@ -51,6 +51,16 @@
|
||||||
};
|
};
|
||||||
|
|
||||||
soc {
|
soc {
|
||||||
|
intc: eru@40044000 {
|
||||||
|
compatible = "infineon,xmc4xxx-intc";
|
||||||
|
reg = <0x40044000 0xff>, <0x50004800 0xff>;
|
||||||
|
/* naming order is intentional. eru1 maps to a lower address than eru0 */
|
||||||
|
reg-names = "eru1", "eru0";
|
||||||
|
interrupts = <1 1>, <2 1>, <3 1>, <4 1>, <5 1>, <6 1>, <7 1>, <8 1>;
|
||||||
|
interrupt-names = "eru0sr0", "eru0sr1", "eru0sr2", "eru0sr3",
|
||||||
|
"eru1sr0", "eru1sr1", "eru1sr2", "eru1sr3";
|
||||||
|
};
|
||||||
|
|
||||||
pinctrl: pinctrl@48028000 {
|
pinctrl: pinctrl@48028000 {
|
||||||
compatible = "infineon,xmc4xxx-pinctrl";
|
compatible = "infineon,xmc4xxx-pinctrl";
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
|
|
|
||||||
22
dts/bindings/interrupt-controller/infineon,xmc4xxx-intc.yaml
Normal file
22
dts/bindings/interrupt-controller/infineon,xmc4xxx-intc.yaml
Normal file
|
|
@ -0,0 +1,22 @@
|
||||||
|
description: Infineon XMC4XXX series Interrupt Controller
|
||||||
|
|
||||||
|
compatible: "infineon,xmc4xxx-intc"
|
||||||
|
|
||||||
|
include: base.yaml
|
||||||
|
|
||||||
|
properties:
|
||||||
|
reg:
|
||||||
|
required: true
|
||||||
|
|
||||||
|
port-line-mapping:
|
||||||
|
type: array
|
||||||
|
required: true
|
||||||
|
description: |
|
||||||
|
An array to store the Event Request Unit (ERU) configuration for a given port/pin
|
||||||
|
combintation. The array elements are opaque fields set using the macro
|
||||||
|
XMC4XXX_INTC_SET_LINE_MAP(port, pin, eru_src, line);
|
||||||
|
eru_src defines where the specific port/pin combination is connected in the ERU.
|
||||||
|
line defines the SR line that will be raised by the event.
|
||||||
|
|
||||||
|
interrupts:
|
||||||
|
required: true
|
||||||
43
include/zephyr/drivers/interrupt_controller/intc_xmc4xxx.h
Normal file
43
include/zephyr/drivers/interrupt_controller/intc_xmc4xxx.h
Normal file
|
|
@ -0,0 +1,43 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2022 Schlumberger
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_XMC4XXX_INTC_H_
|
||||||
|
#define ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_XMC4XXX_INTC_H_
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable interrupt for specific port_id and pin combination
|
||||||
|
*
|
||||||
|
* @param port_id Port index
|
||||||
|
* @param pin pin Pin the port
|
||||||
|
* @param mode Level or edge interrupt
|
||||||
|
* @param trig Trigger edge type (falling, rising or both)
|
||||||
|
* @param fn Callback function
|
||||||
|
* @param user_data Parameter to the interrupt callback
|
||||||
|
*
|
||||||
|
* @retval 0 On success
|
||||||
|
* @retval -ENOTSUP If the specific port_id/pin combination is not supported or
|
||||||
|
* not defined in the dts
|
||||||
|
* @retval -EBUSY If the interrupt line is already used by a different port_id/pin
|
||||||
|
* @retval -EINVAL If the trigger combination is invalid
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
int intc_xmc4xxx_gpio_enable_interrupt(int port_id, int pin, enum gpio_int_mode mode,
|
||||||
|
enum gpio_int_trig trig, void(*fn)(const struct device*, int), void *user_data);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable interrupt for specific port_id and pin combination
|
||||||
|
*
|
||||||
|
* @param port_id Port index
|
||||||
|
* @param pin pin Pin the port
|
||||||
|
* @retval 0 On susccess
|
||||||
|
* @retval -EINVAL If the specific port_id and pin combination has no interrupt
|
||||||
|
* enabled
|
||||||
|
*/
|
||||||
|
|
||||||
|
int intc_xmc4xxx_gpio_disable_interrupt(int port_id, int pin);
|
||||||
|
|
||||||
|
#endif /* ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_XMC4XXX_INTC_H_ */
|
||||||
|
|
@ -0,0 +1,31 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2022 Schlumberger
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: Apache-2.0
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_INFINEON_XMC4XXX_INTC_H_
|
||||||
|
#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_INFINEON_XMC4XXX_INTC_H_
|
||||||
|
|
||||||
|
#define XMC4XXX_INTC_PORT_POS 0
|
||||||
|
#define XMC4XXX_INTC_PORT_MASK 0xf
|
||||||
|
|
||||||
|
#define XMC4XXX_INTC_PIN_POS 4
|
||||||
|
#define XMC4XXX_INTC_PIN_MASK 0xf
|
||||||
|
|
||||||
|
#define XMC4XXX_INTC_LINE_POS 8
|
||||||
|
#define XMC4XXX_INTC_LINE_MASK 0x7
|
||||||
|
|
||||||
|
#define XMC4XXX_INTC_ERU_SRC_POS 11
|
||||||
|
#define XMC4XXX_INTC_ERU_SRC_MASK 0x7
|
||||||
|
|
||||||
|
#define XMC4XXX_INTC_GET_PORT(mx) ((mx >> XMC4XXX_INTC_PORT_POS) & XMC4XXX_INTC_PORT_MASK)
|
||||||
|
#define XMC4XXX_INTC_GET_PIN(mx) ((mx >> XMC4XXX_INTC_PIN_POS) & XMC4XXX_INTC_PIN_MASK)
|
||||||
|
#define XMC4XXX_INTC_GET_LINE(mx) ((mx >> XMC4XXX_INTC_LINE_POS) & XMC4XXX_INTC_LINE_MASK)
|
||||||
|
#define XMC4XXX_INTC_GET_ERU_SRC(mx) ((mx >> XMC4XXX_INTC_ERU_SRC_POS) & XMC4XXX_INTC_ERU_SRC_MASK)
|
||||||
|
|
||||||
|
#define XMC4XXX_INTC_SET_LINE_MAP(port, pin, eru_src, line) \
|
||||||
|
((port) << XMC4XXX_INTC_PORT_POS | (pin) << XMC4XXX_INTC_PIN_POS | \
|
||||||
|
(eru_src) << XMC4XXX_INTC_ERU_SRC_POS | (line) << XMC4XXX_INTC_LINE_POS)
|
||||||
|
|
||||||
|
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_INFINEON_XMC4XXX_INTC_H_ */
|
||||||
|
|
@ -19,4 +19,10 @@ config HAS_XMCLIB_FLASH
|
||||||
bool
|
bool
|
||||||
help
|
help
|
||||||
Enable XMCLIB Flash
|
Enable XMCLIB Flash
|
||||||
|
|
||||||
|
config HAS_XMCLIB_ERU
|
||||||
|
bool
|
||||||
|
help
|
||||||
|
Enable XMCLIB Event Request Unit (ERU) for GPIO interrupt support
|
||||||
|
|
||||||
endif # HAS_XMCLIB
|
endif # HAS_XMCLIB
|
||||||
|
|
|
||||||
|
|
@ -14,5 +14,6 @@ config SOC_SERIES_XMC_4XXX
|
||||||
select CPU_HAS_FPU
|
select CPU_HAS_FPU
|
||||||
select HAS_XMCLIB_UART
|
select HAS_XMCLIB_UART
|
||||||
select HAS_XMCLIB_FLASH
|
select HAS_XMCLIB_FLASH
|
||||||
|
select HAS_XMCLIB_ERU
|
||||||
help
|
help
|
||||||
Enable support for XMC 4xxx MCU series
|
Enable support for XMC 4xxx MCU series
|
||||||
|
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue