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arm: Replace CONFIG_CPU_CORTEX_M0_M0PLUS with CONFIG_ARMV6_M

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Precursor patches have arranged all conditional compilation hanging on
CONFIG_CPU_CORTEX_M0_M0PLUS such that it actually represents support
for ARM ARMv6-M, rename the config variable to reflect this.

Change-Id: I553fcf3e606b350a9e823df31bac96636be1504f
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
This commit is contained in:
Marcus Shawcroft 2016-12-31 14:09:41 +00:00 • committed by Kumar Gala
commit 727dc2c5d6
16 changed files with 93 additions and 93 deletions
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10
arch/arm/core/cortex_m/Kconfig
View file

@ -60,14 +60,14 @@ config CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS
This option signifies the CPU faults other than the hard fault, and
needs to reserve a priority for them.
config CPU_CORTEX_M0_M0PLUS
config ARMV6_M
bool
# Omit prompt to signify "hidden" option
default n
select ATOMIC_OPERATIONS_C
select ISA_THUMB2
help
This option signifies the use of either a Cortex-M0 or Cortex-M0+ CPU.
This option signifies the use of an ARMv6-M processor implementation.
config CPU_CORTEX_M3_M4
bool
@ -83,14 +83,14 @@ config CPU_CORTEX_M3_M4
config CPU_CORTEX_M0
bool
# Omit prompt to signify "hidden" option
select CPU_CORTEX_M0_M0PLUS
select ARMV6_M
help
This option signifies the use of a Cortex-M0 CPU
config CPU_CORTEX_M0PLUS
bool
# Omit prompt to signify "hidden" option
select CPU_CORTEX_M0_M0PLUS
select ARMV6_M
help
This option signifies the use of a Cortex-M0+ CPU
@ -211,7 +211,7 @@ config FLASH_BASE_ADDRESS
endmenu
menu "ARM Cortex-M0/M0+/M3/M4/M7 options"
depends on CPU_CORTEX_M0_M0PLUS || CPU_CORTEX_M3_M4 || CPU_CORTEX_M7
depends on ARMV6_M || CPU_CORTEX_M3_M4 || CPU_CORTEX_M7
config IRQ_OFFLOAD
bool "Enable IRQ offload"

4
arch/arm/core/cortex_m/reset.S
View file

@ -72,14 +72,14 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)
#endif
/* lock interrupts: will get unlocked when switch to main task */
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
cpsid i
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
msr BASEPRI, r0
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
#ifdef CONFIG_WDOG_INIT
/* board-specific watchdog initialization is necessary */

4
arch/arm/core/cortex_m/scb.c
View file

@ -90,7 +90,7 @@ void sys_arch_reboot(int type)
DO_REBOOT();
}
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
/**
*
@ -138,4 +138,4 @@ void _ScbNumPriGroupSet(unsigned int n)
}
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */

4
arch/arm/core/cortex_m/vector_table.S
View file

@ -56,7 +56,7 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,__start)
.word __nmi
.word __hard_fault
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
.word __reserved
.word __reserved
.word __reserved
@ -78,7 +78,7 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,__start)
.word __debug_monitor
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
.word __reserved
.word __pendsv
#if defined(CONFIG_CORTEX_M_SYSTICK)

4
arch/arm/core/cortex_m/vector_table.h
View file

@ -48,7 +48,7 @@ GTEXT(_vector_table)
GTEXT(__reset)
GTEXT(__nmi)
GTEXT(__hard_fault)
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
GTEXT(__mpu_fault)
GTEXT(__bus_fault)
@ -57,7 +57,7 @@ GTEXT(__svc)
GTEXT(__debug_monitor)
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
GTEXT(__pendsv)
GTEXT(__reserved)

8
arch/arm/core/cpu_idle.S
View file

@ -127,7 +127,7 @@ SECTION_FUNC(TEXT, k_cpu_idle)
mov lr, r0
#endif
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
cpsie i
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
/* clear BASEPRI so wfi is awakened by incoming interrupts */
@ -135,7 +135,7 @@ SECTION_FUNC(TEXT, k_cpu_idle)
msr BASEPRI, r0
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
wfi
@ -184,7 +184,7 @@ SECTION_FUNC(TEXT, k_cpu_atomic_idle)
/* r0: interrupt mask from caller */
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
/* No BASEPRI, call wfe directly (SEVONPEND set in _CpuIdleInit()) */
wfe
@ -206,5 +206,5 @@ _irq_disabled:
cpsie i
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
bx lr

20
arch/arm/core/fault.c
View file

@ -69,7 +69,7 @@ void _FaultDump(const NANO_ESF *esf, int fault)
k_current_get(),
esf->pc);
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
int escalation = 0;
@ -103,7 +103,7 @@ void _FaultDump(const NANO_ESF *esf, int fault)
_ScbUsageFaultAllFaultsReset();
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
}
#endif
@ -123,7 +123,7 @@ static void _FaultThreadShow(const NANO_ESF *esf)
k_current_get(), esf->pc);
}
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
/**
@ -250,7 +250,7 @@ static void _DebugMonitor(const NANO_ESF *esf)
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
/**
*
@ -264,7 +264,7 @@ static void _HardFault(const NANO_ESF *esf)
{
PR_EXC("***** HARD FAULT *****\n");
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
_FaultThreadShow(esf);
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
if (_ScbHardFaultIsBusErrOnVectorRead()) {
@ -281,7 +281,7 @@ static void _HardFault(const NANO_ESF *esf)
}
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
}
/**
@ -326,7 +326,7 @@ static void _FaultDump(const NANO_ESF *esf, int fault)
case 3:
_HardFault(esf);
break;
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
case 4:
_MpuFault(esf, 0);
@ -342,7 +342,7 @@ static void _FaultDump(const NANO_ESF *esf, int fault)
break;
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
default:
_ReservedException(esf, fault);
break;
@ -387,10 +387,10 @@ void _Fault(const NANO_ESF *esf)
*/
void _FaultInit(void)
{
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
_ScbDivByZeroFaultEnable();
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
}

12
arch/arm/core/fault_s.S
View file

@ -32,7 +32,7 @@ _ASM_FILE_PROLOGUE
GTEXT(_Fault)
GTEXT(__hard_fault)
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
GTEXT(__mpu_fault)
GTEXT(__bus_fault)
@ -40,7 +40,7 @@ GTEXT(__usage_fault)
GTEXT(__debug_monitor)
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
GTEXT(__reserved)
/**
@ -67,7 +67,7 @@ GTEXT(__reserved)
*/
SECTION_SUBSEC_FUNC(TEXT,__fault,__hard_fault)
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
SECTION_SUBSEC_FUNC(TEXT,__fault,__mpu_fault)
SECTION_SUBSEC_FUNC(TEXT,__fault,__bus_fault)
@ -75,10 +75,10 @@ SECTION_SUBSEC_FUNC(TEXT,__fault,__usage_fault)
SECTION_SUBSEC_FUNC(TEXT,__fault,__debug_monitor)
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
SECTION_SUBSEC_FUNC(TEXT,__fault,__reserved)
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
/* force unlock interrupts */
cpsie i
@ -114,7 +114,7 @@ _stack_frame_endif:
* frame is on the PSP */
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
push {lr}
bl _Fault

12
arch/arm/core/isr_wrapper.S
View file

@ -80,7 +80,7 @@ SECTION_FUNC(TEXT, _isr_wrapper)
ldr r0, [r2, #_kernel_offset_to_idle]
cmp r0, #0
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
beq _idle_state_cleared
movs.n r1, #0
/* clear kernel idle state */
@ -96,13 +96,13 @@ _idle_state_cleared:
blxne _sys_power_save_idle_exit
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
cpsie i /* re-enable interrupts (PRIMASK = 0) */
#endif
mrs r0, IPSR /* get exception number */
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
ldr r1, =16
subs r0, r1 /* get IRQ number */
lsls r0, #3 /* table is 8-byte wide */
@ -111,7 +111,7 @@ _idle_state_cleared:
lsl r0, r0, #3 /* table is 8-byte wide */
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
ldr r1, =_sw_isr_table
add r1, r1, r0 /* table entry: ISRs must have their MSB set to stay
* in thumb mode */
@ -119,14 +119,14 @@ _idle_state_cleared:
ldm r1!,{r0,r3} /* arg in r0, ISR in r3 */
blx r3 /* call ISR */
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
pop {r3}
mov lr, r3
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
pop {lr}
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
/* exception return is done in _IntExit() */
b _IntExit

24
arch/arm/core/swap.S
View file

@ -32,12 +32,12 @@
_ASM_FILE_PROLOGUE
GTEXT(_Swap)
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
GTEXT(__svc)
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
GTEXT(__pendsv)
GDATA(_k_neg_eagain)
@ -77,7 +77,7 @@ SECTION_FUNC(TEXT, __pendsv)
/* save callee-saved + psp in TCS */
mrs ip, PSP
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
/* Store current r4-r7 */
stmea r0!, {r4-r7}
/* copy r8-r12 into r3-r7 */
@ -96,7 +96,7 @@ SECTION_FUNC(TEXT, __pendsv)
#endif /* CONFIG_FP_SHARING */
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
/*
* Prepare to clear PendSV with interrupts unlocked, but
@ -109,14 +109,14 @@ SECTION_FUNC(TEXT, __pendsv)
ldr v3, =_SCS_ICSR_UNPENDSV
/* protect the kernel state while we play with the thread lists */
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
cpsid i
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
msr BASEPRI, r0
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
/* _kernel is still in r1 */
@ -142,7 +142,7 @@ SECTION_FUNC(TEXT, __pendsv)
movs.n r3, #0
str r3, [r2, #_thread_offset_to_basepri]
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
/* BASEPRI not available, previous interrupt disable state
* maps to PRIMASK.
*
@ -184,14 +184,14 @@ _thread_irq_disabled:
ldmia r0, {v1-v8, ip}
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
msr PSP, ip
/* exc return */
bx lr
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
/**
*
@ -249,7 +249,7 @@ _context_switch:
bx lr
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
/**
*
@ -302,7 +302,7 @@ SECTION_FUNC(TEXT, _Swap)
ldr r1, [r1]
str r1, [r2, #_thread_offset_to_swap_return_value]
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
/* No priority-based interrupt masking on M0/M0+,
* pending PendSV is used instead of svc
*/
@ -320,7 +320,7 @@ SECTION_FUNC(TEXT, _Swap)
svc #0
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
/* coming back from exception, r2 still holds the pointer to _current */
ldr r0, [r2, #_thread_offset_to_swap_return_value]