drivers: spi_mcux_lpspi: Clean up DMA path
Clean up DMA path of code. Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This commit is contained in:
Declan Snyder
Anas Nashif
parent
2c884a9274
commit
7271000fe5
1 changed files with 144 additions and 133 deletions
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@ -86,9 +86,7 @@ struct spi_mcux_data {
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struct spi_dma_stream dma_rx;
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struct spi_dma_stream dma_tx;
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/* dummy value used for transferring NOP when tx buf is null */
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uint32_t dummy_tx_buffer;
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/* dummy value used to read RX data into when rx buf is null */
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uint32_t dummy_rx_buffer;
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uint32_t dummy_buffer;
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#endif
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};
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@ -287,179 +285,170 @@ done:
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spi_context_complete(&data->ctx, spi_dev, 0);
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}
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static int spi_mcux_dma_tx_load(const struct device *dev, const uint8_t *buf, size_t len)
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static struct dma_block_config *spi_mcux_dma_common_load(struct spi_dma_stream *stream,
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const struct device *dev,
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const uint8_t *buf, size_t len)
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{
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struct spi_mcux_data *data = dev->data;
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struct dma_block_config *blk_cfg;
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LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
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/* remember active TX DMA channel (used in callback) */
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struct spi_dma_stream *stream = &data->dma_tx;
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blk_cfg = &stream->dma_blk_cfg;
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struct dma_block_config *blk_cfg = &stream->dma_blk_cfg;
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/* prepare the block for this TX DMA channel */
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memset(blk_cfg, 0, sizeof(struct dma_block_config));
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blk_cfg->block_size = len;
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if (buf == NULL) {
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/* Treat the transfer as a peripheral to peripheral one, so that DMA
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* reads from this address each time
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*/
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blk_cfg->source_address = (uint32_t)&data->dummy_tx_buffer;
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blk_cfg->source_address = (uint32_t)&data->dummy_buffer;
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blk_cfg->dest_address = (uint32_t)&data->dummy_buffer;
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/* pretend it is peripheral xfer so DMA just xfer to dummy buf */
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stream->dma_cfg.channel_direction = PERIPHERAL_TO_PERIPHERAL;
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} else {
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/* tx direction has memory as source and periph as dest. */
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blk_cfg->source_address = (uint32_t)buf;
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stream->dma_cfg.channel_direction = MEMORY_TO_PERIPHERAL;
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blk_cfg->dest_address = (uint32_t)buf;
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}
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/* Enable scatter/gather */
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blk_cfg->source_gather_en = 1;
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/* Dest is LPSPI tx fifo */
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blk_cfg->dest_address = LPSPI_GetTxRegisterAddress(base);
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blk_cfg->block_size = len;
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/* Transfer 1 byte each DMA loop */
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stream->dma_cfg.source_burst_length = 1;
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stream->dma_cfg.user_data = (void *)dev;
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stream->dma_cfg.head_block = blk_cfg;
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return blk_cfg;
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}
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static int spi_mcux_dma_tx_load(const struct device *dev, const uint8_t *buf, size_t len)
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{
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LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
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struct spi_mcux_data *data = dev->data;
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/* remember active TX DMA channel (used in callback) */
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struct spi_dma_stream *stream = &data->dma_tx;
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struct dma_block_config *blk_cfg = spi_mcux_dma_common_load(stream, dev, buf, len);
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if (buf != NULL) {
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/* tx direction has memory as source and periph as dest. */
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stream->dma_cfg.channel_direction = MEMORY_TO_PERIPHERAL;
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}
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/* Dest is LPSPI tx fifo */
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blk_cfg->dest_address = LPSPI_GetTxRegisterAddress(base);
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stream->dma_cfg.head_block = &stream->dma_blk_cfg;
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/* give the client dev as arg, as the callback comes from the dma */
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stream->dma_cfg.user_data = (struct device *)dev;
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/* pass our client origin to the dma: data->dma_tx.dma_channel */
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return dma_config(data->dma_tx.dma_dev, data->dma_tx.channel, &stream->dma_cfg);
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return dma_config(stream->dma_dev, stream->channel, &stream->dma_cfg);
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}
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static int spi_mcux_dma_rx_load(const struct device *dev, uint8_t *buf, size_t len)
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{
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struct spi_mcux_data *data = dev->data;
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struct dma_block_config *blk_cfg;
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LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
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struct spi_mcux_data *data = dev->data;
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/* retrieve active RX DMA channel (used in callback) */
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struct spi_dma_stream *stream = &data->dma_rx;
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struct dma_block_config *blk_cfg = spi_mcux_dma_common_load(stream, dev, buf, len);
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blk_cfg = &stream->dma_blk_cfg;
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/* prepare the block for this RX DMA channel */
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memset(blk_cfg, 0, sizeof(struct dma_block_config));
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if (buf == NULL) {
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/* Treat the transfer as a peripheral to peripheral one, so that DMA
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* reads from this address each time
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*/
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blk_cfg->dest_address = (uint32_t)&data->dummy_rx_buffer;
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stream->dma_cfg.channel_direction = PERIPHERAL_TO_PERIPHERAL;
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} else {
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if (buf != NULL) {
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/* rx direction has periph as source and mem as dest. */
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blk_cfg->dest_address = (uint32_t)buf;
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stream->dma_cfg.channel_direction = PERIPHERAL_TO_MEMORY;
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}
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blk_cfg->block_size = len;
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/* Enable scatter/gather */
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blk_cfg->dest_scatter_en = 1;
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/* Source is LPSPI rx fifo */
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blk_cfg->source_address = LPSPI_GetRxRegisterAddress(base);
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stream->dma_cfg.source_burst_length = 1;
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stream->dma_cfg.head_block = blk_cfg;
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stream->dma_cfg.user_data = (struct device *)dev;
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/* pass our client origin to the dma: data->dma_rx.channel */
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return dma_config(data->dma_rx.dma_dev, data->dma_rx.channel, &stream->dma_cfg);
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return dma_config(stream->dma_dev, stream->channel, &stream->dma_cfg);
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}
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static int wait_dma_rx_tx_done(const struct device *dev)
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{
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struct spi_mcux_data *data = dev->data;
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int ret = -1;
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int ret;
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while (1) {
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do {
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ret = spi_context_wait_for_completion(&data->ctx);
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if (ret) {
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LOG_DBG("Timed out waiting for SPI context to complete");
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return ret;
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}
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if (data->status_flags & LPSPI_DMA_ERROR_FLAG) {
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} else if (data->status_flags & LPSPI_DMA_ERROR_FLAG) {
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return -EIO;
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}
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} while (!((data->status_flags & LPSPI_DMA_DONE_FLAG) == LPSPI_DMA_DONE_FLAG));
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if ((data->status_flags & LPSPI_DMA_DONE_FLAG) == LPSPI_DMA_DONE_FLAG) {
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LOG_DBG("DMA block completed");
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return 0;
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}
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}
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}
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static inline int spi_mcux_dma_rxtx_load(const struct device *dev, size_t *dma_size)
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{
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struct spi_mcux_data *lpspi_data = dev->data;
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struct spi_mcux_data *data = dev->data;
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struct spi_context *ctx = &data->ctx;
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int ret = 0;
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/* Clear status flags */
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lpspi_data->status_flags = 0U;
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/* Load dma blocks of equal length */
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*dma_size = MIN(lpspi_data->ctx.tx_len, lpspi_data->ctx.rx_len);
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if (*dma_size == 0) {
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*dma_size = MAX(lpspi_data->ctx.tx_len, lpspi_data->ctx.rx_len);
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}
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data->status_flags = 0U;
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ret = spi_mcux_dma_tx_load(dev, lpspi_data->ctx.tx_buf, *dma_size);
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/* Load dma blocks of equal length */
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*dma_size = spi_context_max_continuous_chunk(ctx);
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ret = spi_mcux_dma_tx_load(dev, ctx->tx_buf, *dma_size);
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if (ret != 0) {
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return ret;
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}
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ret = spi_mcux_dma_rx_load(dev, lpspi_data->ctx.rx_buf, *dma_size);
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ret = spi_mcux_dma_rx_load(dev, ctx->rx_buf, *dma_size);
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if (ret != 0) {
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return ret;
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}
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/* Start DMA */
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ret = dma_start(lpspi_data->dma_tx.dma_dev, lpspi_data->dma_tx.channel);
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ret = dma_start(data->dma_tx.dma_dev, data->dma_tx.channel);
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if (ret != 0) {
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return ret;
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}
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ret = dma_start(lpspi_data->dma_rx.dma_dev, lpspi_data->dma_rx.channel);
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ret = dma_start(data->dma_rx.dma_dev, data->dma_rx.channel);
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return ret;
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}
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static int transceive_dma(const struct device *dev, const struct spi_config *spi_cfg,
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const struct spi_buf_set *tx_bufs, const struct spi_buf_set *rx_bufs,
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bool asynchronous, spi_callback_t cb, void *userdata)
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#ifdef CONFIG_SPI_ASYNC
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static int transceive_dma_async(const struct device *dev, spi_callback_t cb, void *userdata)
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{
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struct spi_mcux_data *data = dev->data;
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LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
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int ret;
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struct spi_context *ctx = &data->ctx;
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size_t dma_size;
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int ret;
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if (!asynchronous) {
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spi_context_lock(&data->ctx, asynchronous, cb, userdata, spi_cfg);
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}
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ctx->asynchronous = true;
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ctx->callback = cb;
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ctx->callback_data = userdata;
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ret = spi_mcux_configure(dev, spi_cfg);
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ret = spi_mcux_dma_rxtx_load(dev, &dma_size);
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if (ret) {
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if (!asynchronous) {
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spi_context_release(&data->ctx, ret);
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}
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return ret;
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}
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#ifdef CONFIG_SOC_SERIES_MCXN
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base->TCR |= LPSPI_TCR_CONT_MASK;
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#endif
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/* Enable DMA Requests */
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LPSPI_EnableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable);
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/* DMA is fast enough watermarks are not required */
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LPSPI_SetFifoWatermarks(base, 0U, 0U);
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return 0;
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}
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#else
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#define transceive_dma_async(...) 0
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#endif /* CONFIG_SPI_ASYNC */
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spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 1);
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static int transceive_dma_sync(const struct device *dev)
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{
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LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
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struct spi_mcux_data *data = dev->data;
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struct spi_context *ctx = &data->ctx;
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size_t dma_size;
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int ret;
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if (!asynchronous) {
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spi_context_cs_control(&data->ctx, true);
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spi_context_cs_control(ctx, true);
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/* Send each spi buf via DMA, updating context as DMA completes */
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while (data->ctx.rx_len > 0 || data->ctx.tx_len > 0) {
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while (ctx->rx_len > 0 || ctx->tx_len > 0) {
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/* Load dma block */
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ret = spi_mcux_dma_rxtx_load(dev, &dma_size);
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if (ret != 0) {
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goto out;
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if (ret) {
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return ret;
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}
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#ifdef CONFIG_SOC_SERIES_MCXN
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@ -473,8 +462,8 @@ static int transceive_dma(const struct device *dev, const struct spi_config *spi
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/* Wait for DMA to finish */
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ret = wait_dma_rx_tx_done(dev);
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if (ret != 0) {
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goto out;
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if (ret) {
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return ret;
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}
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#ifndef CONFIG_SOC_SERIES_MCXN
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@ -487,31 +476,53 @@ static int transceive_dma(const struct device *dev, const struct spi_config *spi
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LPSPI_DisableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable);
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/* Update SPI contexts with amount of data we just sent */
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spi_context_update_tx(&data->ctx, 1, dma_size);
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spi_context_update_rx(&data->ctx, 1, dma_size);
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spi_context_update_tx(ctx, 1, dma_size);
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spi_context_update_rx(ctx, 1, dma_size);
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}
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spi_context_cs_control(&data->ctx, false);
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spi_context_cs_control(ctx, false);
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base->TCR = 0;
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return 0;
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}
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static int transceive_dma(const struct device *dev, const struct spi_config *spi_cfg,
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const struct spi_buf_set *tx_bufs, const struct spi_buf_set *rx_bufs,
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bool asynchronous, spi_callback_t cb, void *userdata)
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{
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struct spi_mcux_data *data = dev->data;
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LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
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int ret;
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if (!asynchronous) {
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spi_context_lock(&data->ctx, asynchronous, cb, userdata, spi_cfg);
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}
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ret = spi_mcux_configure(dev, spi_cfg);
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if (ret && !asynchronous) {
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goto out;
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} else if (ret) {
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return ret;
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}
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#ifdef CONFIG_SOC_SERIES_MCXN
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base->TCR |= LPSPI_TCR_CONT_MASK;
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#endif
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/* DMA is fast enough watermarks are not required */
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LPSPI_SetFifoWatermarks(base, 0U, 0U);
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spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 1);
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if (asynchronous) {
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ret = transceive_dma_async(dev, cb, userdata);
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} else {
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ret = transceive_dma_sync(dev);
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}
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out:
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spi_context_release(&data->ctx, ret);
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}
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#if CONFIG_SPI_ASYNC
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else {
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data->ctx.asynchronous = asynchronous;
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data->ctx.callback = cb;
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data->ctx.callback_data = userdata;
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ret = spi_mcux_dma_rxtx_load(dev, &dma_size);
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if (ret != 0) {
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goto out;
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}
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/* Enable DMA Requests */
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LPSPI_EnableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable);
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}
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#endif
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return ret;
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}
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#else
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