From 7242b567fc14f2699191ec773bf842102a92cc36 Mon Sep 17 00:00:00 2001 From: Guennadi Liakhovetski Date: Mon, 4 Jan 2021 17:22:36 +0100 Subject: [PATCH] cavs: fix LSPGISTS and LSPGCTL access On cAVS 1.8, 2.0 and 2.5 LSPGISTS and LSPGCTL are located in a different shim register range, they cannot be accessed, using the usual SHIM_BASE offset. Signed-off-by: Guennadi Liakhovetski --- soc/xtensa/intel_adsp/cavs_v15/include/soc/shim.h | 1 + soc/xtensa/intel_adsp/cavs_v18/include/soc/shim.h | 4 ---- soc/xtensa/intel_adsp/cavs_v20/include/soc/shim.h | 4 ---- soc/xtensa/intel_adsp/cavs_v25/include/soc/shim.h | 4 ---- soc/xtensa/intel_adsp/common/bootloader/boot_loader.c | 4 ++-- 5 files changed, 3 insertions(+), 14 deletions(-) diff --git a/soc/xtensa/intel_adsp/cavs_v15/include/soc/shim.h b/soc/xtensa/intel_adsp/cavs_v15/include/soc/shim.h index 2338f91afce..bf36b8bd564 100644 --- a/soc/xtensa/intel_adsp/cavs_v15/include/soc/shim.h +++ b/soc/xtensa/intel_adsp/cavs_v15/include/soc/shim.h @@ -204,6 +204,7 @@ #define SHIM_HSPGCTL 0x80 #define SHIM_LSPGCTL 0x84 #define SHIM_SPSREQ 0xa0 +#define LSPGCTL (SHIM_BASE + SHIM_LSPGCTL) #define SHIM_SPSREQ_RVNNP BIT(0) diff --git a/soc/xtensa/intel_adsp/cavs_v18/include/soc/shim.h b/soc/xtensa/intel_adsp/cavs_v18/include/soc/shim.h index 98787f14c46..6ea6641868d 100644 --- a/soc/xtensa/intel_adsp/cavs_v18/include/soc/shim.h +++ b/soc/xtensa/intel_adsp/cavs_v18/include/soc/shim.h @@ -236,10 +236,6 @@ #define LSRMCTL 0x71D54 #define LSPGISTS 0x71D58 -#define SHIM_LSPGCTL 0x50 -#define SHIM_LSPGISTS 0x58 - - #define SHIM_L2_MECS (SHIM_BASE + 0xd0) /** \brief LDO Control */ diff --git a/soc/xtensa/intel_adsp/cavs_v20/include/soc/shim.h b/soc/xtensa/intel_adsp/cavs_v20/include/soc/shim.h index 19bf8952410..42f603b201e 100644 --- a/soc/xtensa/intel_adsp/cavs_v20/include/soc/shim.h +++ b/soc/xtensa/intel_adsp/cavs_v20/include/soc/shim.h @@ -230,10 +230,6 @@ #define LSRMCTL 0x71D54 #define LSPGISTS 0x71D58 -#define SHIM_LSPGCTL 0x50 -#define SHIM_LSPGISTS 0x58 - - #define SHIM_L2_MECS (SHIM_BASE + 0xd0) /** \brief LDO Control */ diff --git a/soc/xtensa/intel_adsp/cavs_v25/include/soc/shim.h b/soc/xtensa/intel_adsp/cavs_v25/include/soc/shim.h index ad097dce5a0..ba44d95ecc8 100644 --- a/soc/xtensa/intel_adsp/cavs_v25/include/soc/shim.h +++ b/soc/xtensa/intel_adsp/cavs_v25/include/soc/shim.h @@ -239,10 +239,6 @@ #define LSRMCTL 0x71D54 #define LSPGISTS 0x71D58 -#define SHIM_LSPGCTL 0x50 -#define SHIM_LSPGISTS 0x58 - - #define SHIM_L2_MECS (SHIM_BASE + 0xd0) /** \brief LDO Control */ diff --git a/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c b/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c index 3319db295ee..3a8eda3da05 100644 --- a/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c +++ b/soc/xtensa/intel_adsp/common/bootloader/boot_loader.c @@ -301,8 +301,8 @@ static int32_t lp_sram_init(void) /* add some delay before writing power registers */ idelay(delay_count); - lspgctl_value = shim_read(SHIM_LSPGISTS); - shim_write(SHIM_LSPGCTL, lspgctl_value & ~LPSRAM_MASK(0)); + lspgctl_value = io_reg_read(LSPGISTS); + io_reg_write(LSPGCTL, lspgctl_value & ~LPSRAM_MASK(0)); /* add some delay before checking the status */ idelay(delay_count);