soc: renesas: ra: Add initial support for RA8M1 SOC series

Add minimal support for RA8M1 SOC series.

Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>

dts/arm/renesas/ra/ra8/r7fa8m1ahecbd.dtsi

@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/renesas/ra/ra8/r7fa8m1xh.dtsi>

dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi

@@ -0,0 +1,202 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/renesas/ra/ra8/ra8x1.dtsi>
+#include <zephyr/dt-bindings/clock/ra_clock.h>
+
+/ {
+	clocks: clocks {
+		xtal: clock-xtal {
+			compatible = "renesas,ra8-cgc-external-clock";
+			clock-frequency = <DT_FREQ_M(20)>;
+			#clock-cells = <0>;
+			status = "disabled";
+		};
+
+		hoco: clock-hoco {
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(48)>;
+			#clock-cells = <0>;
+		};
+
+		moco: clock-moco {
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(8)>;
+			#clock-cells = <0>;
+		};
+
+		loco: clock-loco {
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			#clock-cells = <0>;
+		};
+
+		subclk: clock-subclk {
+			compatible = "renesas,ra8-cgc-subclk";
+			clock-frequency = <32768>;
+			#clock-cells = <0>;
+			status = "disabled";
+		};
+
+		pll: pll {
+			compatible = "renesas,ra8-cgc-pll";
+			#clock-cells = <0>;
+
+			/* PLL */
+			source = <RA_PLL_SOURCE_MAIN_OSC>;
+			div = <RA_PLL_DIV_2>;
+			mul = <96 0>;
+			divp = <RA_PLL_DIV_2>;
+			freqp = <DT_FREQ_M(480)>;
+			divq = <RA_PLL_DIV_2>;
+			freqq = <DT_FREQ_M(480)>;
+			divr = <RA_PLL_DIV_2>;
+			freqr = <DT_FREQ_M(480)>;
+			status = "disabled";
+		};
+
+		pll2: pll2 {
+			compatible = "renesas,ra8-cgc-pll";
+			#clock-cells = <0>;
+
+			/* PLL2 */
+			source = <RA_PLL_SOURCE_DISABLE>;
+			div = <RA_PLL_DIV_2>;
+			mul = <96 0>;
+			divp = <RA_PLL_DIV_2>;
+			freqp = <DT_FREQ_M(0)>;
+			divq = <RA_PLL_DIV_2>;
+			freqq = <DT_FREQ_M(0)>;
+			divr = <RA_PLL_DIV_2>;
+			freqr = <DT_FREQ_M(0)>;
+			status = "disabled";
+		};
+
+		pclkblock: pclkblock {
+			compatible = "renesas,ra8-cgc-pclk-block";
+			#clock-cells = <0>;
+			sysclock-src = <RA_CLOCK_SOURCE_PLL1P>;
+			status = "okay";
+
+			cpuclk: cpuclk {
+				compatible = "renesas,ra8-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_1>;
+				#clock-cells = <0>;
+				status = "okay";
+			};
+
+			iclk: iclk {
+				compatible = "renesas,ra8-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_2>;
+				#clock-cells = <0>;
+				status = "okay";
+			};
+
+			pclka: pclka {
+				compatible = "renesas,ra8-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_4>;
+				#clock-cells = <0>;
+				status = "okay";
+			};
+
+			pclkb: pclkb {
+				compatible = "renesas,ra8-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_8>;
+				#clock-cells = <0>;
+				status = "okay";
+			};
+
+			pclkc: pclkc {
+				compatible = "renesas,ra8-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_8>;
+				#clock-cells = <0>;
+				status = "okay";
+			};
+
+			pclkd: pclkd {
+				compatible = "renesas,ra8-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_4>;
+				#clock-cells = <0>;
+				status = "okay";
+			};
+
+			pclke: pclke {
+				compatible = "renesas,ra8-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_2>;
+				#clock-cells = <0>;
+				status = "okay";
+			};
+
+			bclk: bclk {
+				compatible = "renesas,ra8-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_4>;
+				bclkout: bclkout {
+					compatible = "renesas,ra8-cgc-busclk";
+					clk_out_div = <2>;
+					sdclk = <1>;
+					#clock-cells = <0>;
+				};
+				#clock-cells = <0>;
+				status = "okay";
+			};
+
+			fclk: fclk {
+				compatible = "renesas,ra8-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_8>;
+				#clock-cells = <0>;
+				status = "okay";
+			};
+
+			clkout: clkout {
+				compatible = "renesas,ra8-cgc-pclk";
+				#clock-cells = <0>;
+				status = "disabled";
+			};
+
+			sciclk: sciclk {
+				compatible = "renesas,ra8-cgc-pclk";
+				#clock-cells = <0>;
+				status = "disabled";
+			};
+
+			spiclk: spiclk {
+				compatible = "renesas,ra8-cgc-pclk";
+				#clock-cells = <0>;
+				status = "disabled";
+			};
+
+			canfdclk: canfdclk {
+				compatible = "renesas,ra8-cgc-pclk";
+				#clock-cells = <0>;
+				status = "disabled";
+			};
+
+			i3cclk: i3cclk {
+				compatible = "renesas,ra8-cgc-pclk";
+				#clock-cells = <0>;
+				status = "disabled";
+			};
+
+			uclk: uclk {
+				compatible = "renesas,ra8-cgc-pclk";
+				#clock-cells = <0>;
+				status = "disabled";
+			};
+
+			u60clk: u60clk {
+				compatible = "renesas,ra8-cgc-pclk";
+				#clock-cells = <0>;
+				status = "disabled";
+			};
+
+			octaspiclk: octaspiclk {
+				compatible = "renesas,ra8-cgc-pclk";
+				#clock-cells = <0>;
+				status = "disabled";
+			};
+		};
+	};
+};

dts/arm/renesas/ra/ra8/ra8x1.dtsi

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <arm/armv8.1-m.dtsi>
+#include <freq.h>
+
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m85";
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			mpu: mpu@e000ed90 {
+				compatible = "arm,armv8.1m-mpu";
+				reg = <0xe000ed90 0x40>;
+			};
+		};
+	};
+
+	soc {
+		sram0: memory@22000000 {
+			compatible = "mmio-sram";
+			reg = <0x22000000 DT_SIZE_K(896)>;
+		};
+
+		system: system@4001e000 {
+			compatible = "renesas,ra-system";
+			reg = <0x4001e000 0x1000>;
+			status = "okay";
+		};
+
+		option_setting_ofs: option_setting_ofs@300a100 {
+			compatible = "zephyr,memory-region";
+			reg = <0x0300a100 0x18>;
+			zephyr,memory-region = "OPTION_SETTING_OFS";
+			status = "okay";
+		};
+
+		option_setting_sas: option_setting_sas@300a134 {
+			compatible = "zephyr,memory-region";
+			reg = <0x0300a134 0xcc>;
+			zephyr,memory-region = "OPTION_SETTING_SAS";
+			status = "okay";
+		};
+
+		option_setting_s: option_setting_s@300a200 {
+			compatible = "zephyr,memory-region";
+			reg = <0x0300a200 0x100>;
+			zephyr,memory-region = "OPTION_SETTING_S";
+			status = "okay";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <4>;
+};

dts/bindings/clock/renesas,ra8-cgc-busclk.yaml

@@ -0,0 +1,31 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Renesas RA8 External Bus Clock
+
+compatible: "renesas,ra8-cgc-busclk"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+  clk_out_div:
+    type: int
+    enum:
+    - 0
+    - 1
+    - 2
+    description: |
+      Select EBCLK division ratio from BCLK
+      - 0: disable
+      - 1: EBCLK div/1
+      - 2: EBCLK div/2
+
+  sdclk:
+    type: int
+    enum:
+    - 0
+    - 1
+    description: |
+      SDCLK enable or disable
+      - 0: disable
+      - 1: enable

dts/bindings/clock/renesas,ra8-cgc-external-clock.yaml

@@ -0,0 +1,20 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Renesas RA8 Clock Generation Circuit external clock configuration
+
+compatible: "renesas,ra8-cgc-external-clock"
+
+include: [fixed-clock.yaml, base.yaml]
+
+properties:
+  mosel:
+    type: int
+    default: 0
+    enum:
+      - 0
+      - 1
+    description: |
+      Choose the way for external Clock Oscillator supply
+      0: Resonator
+      1: External clock input

dts/bindings/clock/renesas,ra8-cgc-pclk-block.yaml

@@ -0,0 +1,13 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Renesas RA8 clock control node pclk block
+
+compatible: "renesas,ra8-cgc-pclk-block"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+  sysclock-src:
+    required: true
+    type: int

dts/bindings/clock/renesas,ra8-cgc-pclk.yaml

@@ -0,0 +1,21 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Renesas RA8 Clock Control Peripheral Clock
+
+compatible: "renesas,ra8-cgc-pclk"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+  clk_src:
+    type: int
+
+  clk_div:
+    type: int
+    required: true
+    description: Prescale divider to calculate the subclock frequency from the
+                 system clock frequency.
+
+  "#clock-cells":
+    const: 0

dts/bindings/clock/renesas,ra8-cgc-pll.yaml

@@ -0,0 +1,36 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Renesas RA8 Clock Generation Circuit PLL Clock
+
+compatible: "renesas,ra8-cgc-pll"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+  source:
+    required: true
+    type: int
+  div:
+    required: true
+    type: int
+  mul:
+    required: true
+    type: array
+  divp:
+    required: true
+    type: int
+  freqp:
+    required: true
+    type: int
+  divq:
+    type: int
+  freqq:
+    type: int
+  divr:
+    type: int
+  freqr:
+    type: int
+
+  "#clock-cells":
+    const: 0

dts/bindings/clock/renesas,ra8-cgc-subclk.yaml

@@ -0,0 +1,30 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Renesas RA8 Sub-Clock
+
+compatible: "renesas,ra8-cgc-subclk"
+
+include: fixed-clock.yaml
+
+properties:
+  drive-capability:
+    type: int
+    default: 0
+    enum:
+    - 0
+    - 1
+    - 2
+    - 3
+    description: |
+      Sub-Clock Oscillator Drive Capability Switching
+      - 0: Standard (12.5pf)
+      - 1: Lowpower mode 1 (9pf)
+      - 2: Lowpower mode 2 (7pf)
+      - 3: Lowpower mode 3 (4pf)
+
+  stabilization-time:
+    type: int
+    default: 1000
+    description: |
+      Sub-Clock stabilization time in micro seconds

include/zephyr/dt-bindings/clock/ra_clock.h

@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RA_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RA_H_
+
+#define RA_PLL_SOURCE_HOCO     0
+#define RA_PLL_SOURCE_MOCO     1
+#define RA_PLL_SOURCE_LOCO     2
+#define RA_PLL_SOURCE_MAIN_OSC 3
+#define RA_PLL_SOURCE_SUBCLOCK 4
+#define RA_PLL_SOURCE_DISABLE  0xff
+
+#define RA_CLOCK_SOURCE_HOCO     0
+#define RA_CLOCK_SOURCE_MOCO     1
+#define RA_CLOCK_SOURCE_LOCO     2
+#define RA_CLOCK_SOURCE_MAIN_OSC 3
+#define RA_CLOCK_SOURCE_SUBCLOCK 4
+#define RA_CLOCK_SOURCE_PLL      5
+#define RA_CLOCK_SOURCE_PLL1P    RA_CLOCK_SOURCE_PLL
+#define RA_CLOCK_SOURCE_PLL2     6
+#define RA_CLOCK_SOURCE_PLL2P    RA_CLOCK_SOURCE_PLL2
+#define RA_CLOCK_SOURCE_PLL1Q    7
+#define RA_CLOCK_SOURCE_PLL1R    8
+#define RA_CLOCK_SOURCE_PLL2Q    9
+#define RA_CLOCK_SOURCE_PLL2R    10
+#define RA_CLOCK_SOURCE_DISABLE  0xff
+
+#define RA_SYS_CLOCK_DIV_1   0
+#define RA_SYS_CLOCK_DIV_2   1
+#define RA_SYS_CLOCK_DIV_4   2
+#define RA_SYS_CLOCK_DIV_8   3
+#define RA_SYS_CLOCK_DIV_16  4
+#define RA_SYS_CLOCK_DIV_32  5
+#define RA_SYS_CLOCK_DIV_64  6
+#define RA_SYS_CLOCK_DIV_128 7 /* available for CLKOUT only */
+#define RA_SYS_CLOCK_DIV_3   8
+#define RA_SYS_CLOCK_DIV_6   9
+#define RA_SYS_CLOCK_DIV_12  10
+
+/* PLL divider options. */
+#define RA_PLL_DIV_1  0
+#define RA_PLL_DIV_2  1
+#define RA_PLL_DIV_3  2
+#define RA_PLL_DIV_4  3
+#define RA_PLL_DIV_5  4
+#define RA_PLL_DIV_6  5
+#define RA_PLL_DIV_8  7
+#define RA_PLL_DIV_9  8
+#define RA_PLL_DIV_16 15
+
+/* USB clock divider options. */
+#define RA_USB_CLOCK_DIV_1 0
+#define RA_USB_CLOCK_DIV_2 1
+#define RA_USB_CLOCK_DIV_3 2
+#define RA_USB_CLOCK_DIV_4 3
+#define RA_USB_CLOCK_DIV_5 4
+#define RA_USB_CLOCK_DIV_6 5
+#define RA_USB_CLOCK_DIV_8 7
+
+/* USB60 clock divider options. */
+#define RA_USB60_CLOCK_DIV_1 0
+#define RA_USB60_CLOCK_DIV_2 1
+#define RA_USB60_CLOCK_DIV_3 5
+#define RA_USB60_CLOCK_DIV_4 2
+#define RA_USB60_CLOCK_DIV_5 6
+#define RA_USB60_CLOCK_DIV_6 3
+#define RA_USB60_CLOCK_DIV_8 4
+
+/* OCTA clock divider options. */
+#define RA_OCTA_CLOCK_DIV_1 0
+#define RA_OCTA_CLOCK_DIV_2 1
+#define RA_OCTA_CLOCK_DIV_4 2
+#define RA_OCTA_CLOCK_DIV_6 3
+#define RA_OCTA_CLOCK_DIV_8 4
+
+/* CANFD clock divider options. */
+#define RA_CANFD_CLOCK_DIV_1 0
+#define RA_CANFD_CLOCK_DIV_2 1
+#define RA_CANFD_CLOCK_DIV_3 5
+#define RA_CANFD_CLOCK_DIV_4 2
+#define RA_CANFD_CLOCK_DIV_5 6
+#define RA_CANFD_CLOCK_DIV_6 3
+#define RA_CANFD_CLOCK_DIV_8 4
+
+/* SCI clock divider options. */
+#define RA_SCI_CLOCK_DIV_1 0
+#define RA_SCI_CLOCK_DIV_2 1
+#define RA_SCI_CLOCK_DIV_3 5
+#define RA_SCI_CLOCK_DIV_4 2
+#define RA_SCI_CLOCK_DIV_5 6
+#define RA_SCI_CLOCK_DIV_6 3
+#define RA_SCI_CLOCK_DIV_8 4
+
+/* SPI clock divider options. */
+#define RA_SPI_CLOCK_DIV_1 0
+#define RA_SPI_CLOCK_DIV_2 1
+#define RA_SPI_CLOCK_DIV_3 5
+#define RA_SPI_CLOCK_DIV_4 2
+#define RA_SPI_CLOCK_DIV_5 6
+#define RA_SPI_CLOCK_DIV_6 3
+#define RA_SPI_CLOCK_DIV_8 4
+
+/* CEC clock divider options. */
+#define RA_CEC_CLOCK_DIV_1 0
+#define RA_CEC_CLOCK_DIV_2 1
+
+/* I3C clock divider options. */
+#define RA_I3C_CLOCK_DIV_1 0
+#define RA_I3C_CLOCK_DIV_2 1
+#define RA_I3C_CLOCK_DIV_3 5
+#define RA_I3C_CLOCK_DIV_4 2
+#define RA_I3C_CLOCK_DIV_5 6
+#define RA_I3C_CLOCK_DIV_6 3
+#define RA_I3C_CLOCK_DIV_8 4
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RA_H_ */

modules/Kconfig

@@ -28,6 +28,7 @@ source "modules/Kconfig.nuvoton"
 source "modules/Kconfig.open-amp"
 source "modules/Kconfig.picolibc"
 source "modules/Kconfig.nxp_s32"
+source "modules/Kconfig.renesas_fsp"
 source "modules/Kconfig.silabs"
 source "modules/Kconfig.simplelink"
 source "modules/Kconfig.sof"

modules/Kconfig.renesas_fsp

@@ -0,0 +1,9 @@
+# Renesas FSP HAL config
+
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config HAS_RENESAS_RA_FSP
+	bool
+	help
+	  Enable Renesas RA FSP support

soc/renesas/ra/CMakeLists.txt

@@ -1,6 +1,8 @@
 # Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
+# Copyright (c) 2024 Renesas Electronics Corporation
 # SPDX-License-Identifier: Apache-2.0
 
 zephyr_include_directories(common)
+zephyr_include_directories_ifdef(CONFIG_HAS_RENESAS_RA_FSP common_fsp)
 
 add_subdirectory(${SOC_SERIES})

soc/renesas/ra/common_fsp/vector_data.h

@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Keep for bsp_api.h */
+
+#ifndef ZEPHYR_SOC_RENESAS_RA_COMMON_VECTOR_DATA_H_
+#define ZEPHYR_SOC_RENESAS_RA_COMMON_VECTOR_DATA_H_
+
+#endif /* ZEPHYR_SOC_RENESAS_RA_COMMON_VECTOR_DATA_H_ */

soc/renesas/ra/ra8m1/CMakeLists.txt

@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+zephyr_sources(
+  soc.c
+)
+
+zephyr_linker_sources(SECTIONS sections.ld)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

soc/renesas/ra/ra8m1/Kconfig

@@ -0,0 +1,16 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RA8M1
+	select ARM
+	select CPU_CORTEX_M85
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_FPU
+	select CPU_HAS_ARM_SAU
+	select ARMV8_M_DSP
+	select FPU
+	select HAS_SWO
+	select XIP
+	select HAS_RENESAS_RA_FSP
+	help
+	  Enable support for Renesas RA8M1 MCU series

soc/renesas/ra/ra8m1/Kconfig.defconfig

@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_RA8M1
+
+config NUM_IRQS
+	default 96
+
+config PINCTRL
+	default y
+
+endif # SOC_SERIES_RA8M1

soc/renesas/ra/ra8m1/Kconfig.soc

@@ -0,0 +1,21 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+
+config SOC_SERIES_RA8M1
+	bool
+	select SOC_FAMILY_RENESAS_RA
+	help
+	  Renesas RA8M1 series
+
+config SOC_R7FA8M1AHECBD
+	bool
+	select SOC_SERIES_RA8M1
+	help
+	  R7FA8M1AHECBD
+
+config SOC_SERIES
+	default "ra8m1" if SOC_SERIES_RA8M1
+
+config SOC
+	default "r7fa8m1ahecbd" if SOC_R7FA8M1AHECBD

soc/renesas/ra/ra8m1/sections.ld

@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+.code_in_ram :
+{
+	. = ALIGN(4);
+	__Code_In_RAM_Start = .;
+	KEEP(*(.code_in_ram*))
+	__Code_In_RAM_End = .;
+} > RAMABLE_REGION
+
+SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
+{
+	/* If DTC is used, put the DTC vector table at the start of SRAM.
+		This avoids memory holes due to 1K alignment required by it. */
+	*(.fsp_dtc_vector_table)
+} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
+
+SECTION_PROLOGUE(.option_setting_ofs,,)
+{
+	__OPTION_SETTING_OFS_Start = .;
+	KEEP(*(.option_setting_ofs0))
+	. = __OPTION_SETTING_OFS_Start + 0x04;
+	KEEP(*(.option_setting_ofs2))
+	. = __OPTION_SETTING_OFS_Start + 0x10;
+	KEEP(*(.option_setting_dualsel))
+	__OPTION_SETTING_OFS_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
+
+SECTION_PROLOGUE(.option_setting_sas,,)
+{
+	__OPTION_SETTING_SAS_Start = .;
+	KEEP(*(.option_setting_sas))
+	__OPTION_SETTING_SAS_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
+
+SECTION_PROLOGUE(.option_setting_s,,)
+{
+	__OPTION_SETTING_S_Start = .;
+	KEEP(*(.option_setting_ofs1_sec))
+	. = __OPTION_SETTING_S_Start + 0x04;
+	KEEP(*(.option_setting_ofs3_sec))
+	. = __OPTION_SETTING_S_Start + 0x10;
+	KEEP(*(.option_setting_banksel_sec))
+	. = __OPTION_SETTING_S_Start + 0x40;
+	KEEP(*(.option_setting_bps_sec0))
+	. = __OPTION_SETTING_S_Start + 0x44;
+	KEEP(*(.option_setting_bps_sec1))
+	. = __OPTION_SETTING_S_Start + 0x48;
+	KEEP(*(.option_setting_bps_sec2))
+	. = __OPTION_SETTING_S_Start + 0x4C;
+	KEEP(*(.option_setting_bps_sec3))
+	. = __OPTION_SETTING_S_Start + 0x60;
+	KEEP(*(.option_setting_pbps_sec0))
+	. = __OPTION_SETTING_S_Start + 0x64;
+	KEEP(*(.option_setting_pbps_sec1))
+	. = __OPTION_SETTING_S_Start + 0x68;
+	KEEP(*(.option_setting_pbps_sec2))
+	. = __OPTION_SETTING_S_Start + 0x6C;
+	KEEP(*(.option_setting_pbps_sec3))
+	. = __OPTION_SETTING_S_Start + 0x80;
+	KEEP(*(.option_setting_ofs1_sel))
+	. = __OPTION_SETTING_S_Start + 0x84;
+	KEEP(*(.option_setting_ofs3_sel))
+	. = __OPTION_SETTING_S_Start + 0x90;
+	KEEP(*(.option_setting_banksel_sel))
+	. = __OPTION_SETTING_S_Start + 0xC0;
+	KEEP(*(.option_setting_bps_sel0))
+	. = __OPTION_SETTING_S_Start + 0xC4;
+	KEEP(*(.option_setting_bps_sel1))
+	. = __OPTION_SETTING_S_Start + 0xC8;
+	KEEP(*(.option_setting_bps_sel2))
+	. = __OPTION_SETTING_S_Start + 0xCC;
+	KEEP(*(.option_setting_bps_sel3))
+	__OPTION_SETTING_S_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF

soc/renesas/ra/ra8m1/soc.c

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for Renesas RA8M1 family processor
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/arch/cpu.h>
+#include <cmsis_core.h>
+#include <zephyr/arch/arm/nmi.h>
+#include <zephyr/irq.h>
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
+
+#include <bsp_api.h>
+
+uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ * So the init priority has to be 0 (zero).
+ *
+ * @return 0
+ */
+static int renesas_ra8m1_init(void)
+{
+	SystemCoreClock = BSP_MOCO_HZ;
+	bsp_clock_init();
+
+	return 0;
+}
+
+SYS_INIT(renesas_ra8m1_init, PRE_KERNEL_1, 0);

soc/renesas/ra/ra8m1/soc.h

@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file SoC configuration macros for the Renesas RA8M1 family MCU
+ */
+
+#ifndef ZEPHYR_SOC_RENESAS_RA8M1_SOC_H_
+#define ZEPHYR_SOC_RENESAS_RA8M1_SOC_H_
+
+#include <bsp_api.h>
+
+#endif /* ZEPHYR_SOC_RENESAS_RA8M1_SOC_H_ */

soc/renesas/ra/soc.yml

@@ -4,3 +4,6 @@ family:
       - name: ra4m1
         socs:
           - name: r7fa4m1ab3cfm
+      - name: ra8m1
+        socs:
+          - name: r7fa8m1ahecbd