timer: mchp_xec_rtos: convert to use DT_INST_ defines
Use DT_INST_* instead of the hard-coded macro from the HAL, as DT_INST_* are preferred. Fixes #17775 Signed-off-by: Daniel Leung <daniel.leung@intel.com>
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90ac56100c
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711f88a9bc
1 changed files with 26 additions and 16 deletions
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@ -47,6 +47,9 @@ BUILD_ASSERT_MSG(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC == 32768,
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#define CYCLES_PER_TICK \
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(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC)
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#define TIMER_REGS \
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((RTMR_Type *) DT_INST_0_MICROCHIP_XEC_RTOS_TIMER_BASE_ADDRESS)
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/* Mask off bits[31:28] of 32-bit count */
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#define TIMER_MAX 0x0FFFFFFFUL
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@ -76,10 +79,10 @@ static u32_t cached_icr = CYCLES_PER_TICK;
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static void timer_restart(u32_t countdown)
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{
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RTMR_REGS->CTRL = 0U;
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RTMR_REGS->CTRL = MCHP_RTMR_CTRL_BLK_EN;
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RTMR_REGS->PRLD = countdown;
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RTMR_REGS->CTRL = TIMER_START_VAL;
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TIMER_REGS->CTRL = 0U;
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TIMER_REGS->CTRL = MCHP_RTMR_CTRL_BLK_EN;
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TIMER_REGS->PRLD = countdown;
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TIMER_REGS->CTRL = TIMER_START_VAL;
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}
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/*
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@ -96,9 +99,9 @@ static void timer_restart(u32_t countdown)
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*/
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static INLINE u32_t timer_count(void)
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{
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u32_t ccr = RTMR_REGS->CNT;
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u32_t ccr = TIMER_REGS->CNT;
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if ((ccr == 0) && (RTMR_REGS->CTRL & MCHP_RTMR_CTRL_START)) {
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if ((ccr == 0) && (TIMER_REGS->CTRL & MCHP_RTMR_CTRL_START)) {
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ccr = cached_icr;
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}
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@ -135,7 +138,7 @@ void z_clock_set_timeout(s32_t n, bool idle)
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* We are not in a locked section. Are writes to two
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* global objects safe from pre-emption?
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*/
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RTMR_REGS->CTRL = 0U; /* stop timer */
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TIMER_REGS->CTRL = 0U; /* stop timer */
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cached_icr = TIMER_STOPPED;
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return;
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}
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@ -155,8 +158,9 @@ void z_clock_set_timeout(s32_t n, bool idle)
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ccr = timer_count();
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/* turn off to clear any pending interrupt status */
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RTMR_REGS->CTRL = 0U;
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GIRQ23_REGS->SRC = MCHP_RTMR_GIRQ_VAL;
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TIMER_REGS->CTRL = 0U;
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MCHP_GIRQ_SRC(DT_INST_0_MICROCHIP_XEC_RTOS_TIMER_GIRQ) =
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BIT(DT_INST_0_MICROCHIP_XEC_RTOS_TIMER_GIRQ_BIT);
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NVIC_ClearPendingIRQ(RTMR_IRQn);
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temp = total_cycles;
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@ -216,7 +220,9 @@ static void xec_rtos_timer_isr(void *arg)
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k_spinlock_key_t key = k_spin_lock(&lock);
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GIRQ23_REGS->SRC = MCHP_RTMR_GIRQ_VAL;
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MCHP_GIRQ_SRC(DT_INST_0_MICROCHIP_XEC_RTOS_TIMER_GIRQ) =
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BIT(DT_INST_0_MICROCHIP_XEC_RTOS_TIMER_GIRQ_BIT);
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/* Restart the timer as early as possible to minimize drift... */
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timer_restart(MAX_TICKS * CYCLES_PER_TICK);
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@ -247,7 +253,9 @@ static void xec_rtos_timer_isr(void *arg)
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k_spinlock_key_t key = k_spin_lock(&lock);
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GIRQ23_REGS->SRC = MCHP_RTMR_GIRQ_VAL;
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MCHP_GIRQ_SRC(DT_INST_0_MICROCHIP_XEC_RTOS_TIMER_GIRQ) =
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BIT(DT_INST_0_MICROCHIP_XEC_RTOS_TIMER_GIRQ_BIT);
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/* Restart the timer as early as possible to minimize drift... */
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timer_restart(cached_icr);
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@ -301,7 +309,7 @@ void z_clock_idle_exit(void)
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void sys_clock_disable(void)
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{
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RTMR_REGS->CTRL = 0U;
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TIMER_REGS->CTRL = 0U;
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}
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int z_clock_driver_init(struct device *device)
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@ -314,15 +322,17 @@ int z_clock_driver_init(struct device *device)
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cached_icr = MAX_TICKS;
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#endif
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RTMR_REGS->CTRL = 0U;
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GIRQ23_REGS->SRC = MCHP_RTMR_GIRQ_VAL;
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TIMER_REGS->CTRL = 0U;
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MCHP_GIRQ_SRC(DT_INST_0_MICROCHIP_XEC_RTOS_TIMER_GIRQ) =
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BIT(DT_INST_0_MICROCHIP_XEC_RTOS_TIMER_GIRQ_BIT);
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NVIC_ClearPendingIRQ(RTMR_IRQn);
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IRQ_CONNECT(RTMR_IRQn,
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DT_INST_0_MICROCHIP_XEC_RTOS_TIMER_IRQ_0_PRIORITY,
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xec_rtos_timer_isr, 0, 0);
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GIRQ23_REGS->EN_SET = MCHP_RTMR_GIRQ_VAL;
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MCHP_GIRQ_ENSET(DT_INST_0_MICROCHIP_XEC_RTOS_TIMER_GIRQ) =
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BIT(DT_INST_0_MICROCHIP_XEC_RTOS_TIMER_GIRQ_BIT);
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irq_enable(RTMR_IRQn);
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#ifdef CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT
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@ -337,7 +347,7 @@ int z_clock_driver_init(struct device *device)
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timer_restart(cached_icr);
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/* wait for Hibernation timer to load count register from preload */
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while (RTMR_REGS->CNT == 0)
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while (TIMER_REGS->CNT == 0)
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;
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B32TMR0_REGS->CTRL = btmr_ctrl;
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#else
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