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arm: soc: move arm SoCs to top-dir

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Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2018-09-03 15:47:02 -05:00
commit 70d819b405
426 changed files with 62 additions and 63 deletions
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5
soc/arm/st_stm32/stm32l4/CMakeLists.txt Normal file
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zephyr_include_directories(${ZEPHYR_BASE}/drivers)
zephyr_sources(
soc.c
)
zephyr_sources_ifdef(CONFIG_GPIO soc_gpio.c)

37
soc/arm/st_stm32/stm32l4/Kconfig.defconfig.series Normal file
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# Kconfig - ST Microelectronics STM32L4 MCU line
#
# Copyright (c) 2016 Open-RnD Sp. z o.o.
# Copyright (c) 2016 BayLibre, SAS
#
# SPDX-License-Identifier: Apache-2.0
#
if SOC_SERIES_STM32L4X
source "soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4*"
config SOC_SERIES
default "stm32l4"
if I2C_STM32
config I2C_STM32_V2
def_bool y
endif # I2C_STM32
if ENTROPY_GENERATOR
config ENTROPY_STM32_RNG
def_bool y
endif # ENTROPY_GENERATOR
if RTC
config RTC_STM32
default y
endif # RTC
endif # SOC_SERIES_STM32L4X

27
soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l432xx Normal file
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# Kconfig - ST Microelectronics STM32L432XX MCU
#
# Copyright (c) 2016 Open-RnD Sp. z o.o.
# Copyright (c) 2016 BayLibre, SAS
#
# SPDX-License-Identifier: Apache-2.0
#
if SOC_STM32L432XC
config SOC
string
default "stm32l432xx"
config NUM_IRQS
int
default 83
if GPIO_STM32
config GPIO_STM32_PORTH
default y
endif # GPIO_STM32
endif # SOC_STM32L432XC

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soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l433xx Normal file
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# Kconfig - ST Microelectronics STM32L433XX MCU
#
# Copyright (c) 2018 David Lamparter
#
# SPDX-License-Identifier: Apache-2.0
#
if SOC_STM32L433XC
config SOC
string
default "stm32l433xx"
config NUM_IRQS
int
default 83
if GPIO_STM32
config GPIO_STM32_PORTD
def_bool y
config GPIO_STM32_PORTE
default y
config GPIO_STM32_PORTH
default y
endif # GPIO_STM32
endif # SOC_STM32L433XC

37
soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l475xg Normal file
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# Kconfig - ST Microelectronics STM32L475xG MCU
#
# Copyright (c) 2017 Linaro Limited
#
# SPDX-License-Identifier: Apache-2.0
#
if SOC_STM32L475XG
config SOC
string
default "stm32l475xx"
config NUM_IRQS
int
default 82
if GPIO_STM32
config GPIO_STM32_PORTD
def_bool y
config GPIO_STM32_PORTE
default y
config GPIO_STM32_PORTF
default y
config GPIO_STM32_PORTG
default y
config GPIO_STM32_PORTH
default y
endif # GPIO_STM32
endif # SOC_STM32L475XG

38
soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l476xx Normal file
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# Kconfig - ST Microelectronics STM32L476RG MCU
#
# Copyright (c) 2016 Open-RnD Sp. z o.o.
# Copyright (c) 2016 BayLibre, SAS
#
# SPDX-License-Identifier: Apache-2.0
#
if SOC_STM32L476XG
config SOC
string
default "stm32l476xx"
config NUM_IRQS
int
default 82
if GPIO_STM32
config GPIO_STM32_PORTD
def_bool y
config GPIO_STM32_PORTE
default y
config GPIO_STM32_PORTF
default y
config GPIO_STM32_PORTG
default y
config GPIO_STM32_PORTH
default y
endif # GPIO_STM32
endif # SOC_STM32L476XG

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soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l496xx Normal file
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# Kconfig - ST Microelectronics STM32L496xx MCU
#
# Copyright (c) 2016 Open-RnD Sp. z o.o.
# Copyright (c) 2016 BayLibre, SAS
#
# SPDX-License-Identifier: Apache-2.0
#
if SOC_STM32L496XG
config SOC
string
default "stm32l496xx"
config NUM_IRQS
int
default 91
if GPIO_STM32
config GPIO_STM32_PORTD
def_bool y
config GPIO_STM32_PORTE
default y
config GPIO_STM32_PORTF
default y
config GPIO_STM32_PORTG
default y
config GPIO_STM32_PORTH
default y
config GPIO_STM32_PORTI
default y
endif # GPIO_STM32
endif # SOC_STM32L496XG

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soc/arm/st_stm32/stm32l4/Kconfig.series Normal file
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# Kconfig - ST Microelectronics STM32L4 MCU series
#
# Copyright (c) 2016 Open-RnD Sp. z o.o.
# Copyright (c) 2016 BayLibre, SAS
#
# SPDX-License-Identifier: Apache-2.0
#
config SOC_SERIES_STM32L4X
bool "STM32L4x Series MCU"
select CPU_CORTEX_M4
select CPU_HAS_FPU
select SOC_FAMILY_STM32
select SYS_POWER_LOW_POWER_STATE_SUPPORTED
select HAS_STM32CUBE
select CPU_HAS_MPU
select CPU_HAS_SYSTICK
select CLOCK_CONTROL_STM32_CUBE if CLOCK_CONTROL
help
Enable support for STM32L4 MCU series

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soc/arm/st_stm32/stm32l4/Kconfig.soc Normal file
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# Kconfig - ST Microelectronics STM32L4 MCU line
#
# Copyright (c) 2016 Open-RnD Sp. z o.o.
# Copyright (c) 2016 BayLibre, SAS
#
# SPDX-License-Identifier: Apache-2.0
#
choice
prompt "STM32L4x MCU Selection"
depends on SOC_SERIES_STM32L4X
config SOC_STM32L476XG
bool "STM32L476XG"
config SOC_STM32L496XG
bool "STM32L496XG"
config SOC_STM32L432XC
bool "STM32L432XC"
config SOC_STM32L433XC
bool "STM32L433XC"
config SOC_STM32L475XG
bool "STM32L475XG"
endchoice

160
soc/arm/st_stm32/stm32l4/dts.fixup Normal file
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/* SoC level DTS fixup file */
#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
#define CONFIG_UART_STM32_USART_1_BASE_ADDRESS ST_STM32_USART_40013800_BASE_ADDRESS
#define CONFIG_UART_STM32_USART_1_BAUD_RATE ST_STM32_USART_40013800_CURRENT_SPEED
#define CONFIG_UART_STM32_USART_1_IRQ_PRI ST_STM32_USART_40013800_IRQ_0_PRIORITY
#define CONFIG_UART_STM32_USART_1_NAME ST_STM32_USART_40013800_LABEL
#define USART_1_IRQ ST_STM32_USART_40013800_IRQ_0
#define CONFIG_UART_STM32_USART_2_BASE_ADDRESS ST_STM32_USART_40004400_BASE_ADDRESS
#define CONFIG_UART_STM32_USART_2_BAUD_RATE ST_STM32_USART_40004400_CURRENT_SPEED
#define CONFIG_UART_STM32_USART_2_IRQ_PRI ST_STM32_USART_40004400_IRQ_0_PRIORITY
#define CONFIG_UART_STM32_USART_2_NAME ST_STM32_USART_40004400_LABEL
#define USART_2_IRQ ST_STM32_USART_40004400_IRQ_0
#define CONFIG_UART_STM32_USART_3_BASE_ADDRESS ST_STM32_USART_40004800_BASE_ADDRESS
#define CONFIG_UART_STM32_USART_3_BAUD_RATE ST_STM32_USART_40004800_CURRENT_SPEED
#define CONFIG_UART_STM32_USART_3_IRQ_PRI ST_STM32_USART_40004800_IRQ_0_PRIORITY
#define CONFIG_UART_STM32_USART_3_NAME ST_STM32_USART_40004800_LABEL
#define USART_3_IRQ ST_STM32_USART_40004800_IRQ_0
#define CONFIG_UART_STM32_UART_4_BASE_ADDRESS ST_STM32_UART_40004C00_BASE_ADDRESS
#define CONFIG_UART_STM32_UART_4_BAUD_RATE ST_STM32_UART_40004C00_CURRENT_SPEED
#define CONFIG_UART_STM32_UART_4_IRQ_PRI ST_STM32_UART_40004C00_IRQ_0_PRIORITY
#define CONFIG_UART_STM32_UART_4_NAME ST_STM32_UART_40004C00_LABEL
#define UART_4_IRQ ST_STM32_UART_40004C00_IRQ_0
#define CONFIG_UART_STM32_UART_5_BASE_ADDRESS ST_STM32_UART_40005000_BASE_ADDRESS
#define CONFIG_UART_STM32_UART_5_BAUD_RATE ST_STM32_UART_40005000_CURRENT_SPEED
#define CONFIG_UART_STM32_UART_5_IRQ_PRI ST_STM32_UART_40005000_IRQ_0_PRIORITY
#define CONFIG_UART_STM32_UART_5_NAME ST_STM32_UART_40005000_LABEL
#define UART_5_IRQ ST_STM32_UART_40005000_IRQ_0
#define CONFIG_UART_STM32_LPUART_1_BASE_ADDRESS ST_STM32_LPUART_40008000_BASE_ADDRESS
#define CONFIG_UART_STM32_LPUART_1_BAUD_RATE ST_STM32_LPUART_40008000_CURRENT_SPEED
#define CONFIG_UART_STM32_LPUART_1_IRQ_PRI ST_STM32_LPUART_40008000_IRQ_0_PRIORITY
#define CONFIG_UART_STM32_LPUART_1_NAME ST_STM32_LPUART_40008000_LABEL
#define LPUART_1_IRQ ST_STM32_LPUART_40008000_IRQ_0
#define CONFIG_I2C_1_BASE_ADDRESS ST_STM32_I2C_V2_40005400_BASE_ADDRESS
#define CONFIG_I2C_1_EVENT_IRQ_PRI ST_STM32_I2C_V2_40005400_IRQ_EVENT_PRIORITY
#define CONFIG_I2C_1_ERROR_IRQ_PRI ST_STM32_I2C_V2_40005400_IRQ_ERROR_PRIORITY
#define CONFIG_I2C_1_NAME ST_STM32_I2C_V2_40005400_LABEL
#define CONFIG_I2C_1_EVENT_IRQ ST_STM32_I2C_V2_40005400_IRQ_EVENT
#define CONFIG_I2C_1_ERROR_IRQ ST_STM32_I2C_V2_40005400_IRQ_ERROR
#define CONFIG_I2C_1_BITRATE ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY
#define CONFIG_I2C_2_BASE_ADDRESS ST_STM32_I2C_V2_40005800_BASE_ADDRESS
#define CONFIG_I2C_2_EVENT_IRQ_PRI ST_STM32_I2C_V2_40005800_IRQ_EVENT_PRIORITY
#define CONFIG_I2C_2_ERROR_IRQ_PRI ST_STM32_I2C_V2_40005800_IRQ_ERROR_PRIORITY
#define CONFIG_I2C_2_NAME ST_STM32_I2C_V2_40005800_LABEL
#define CONFIG_I2C_2_EVENT_IRQ ST_STM32_I2C_V2_40005800_IRQ_EVENT
#define CONFIG_I2C_2_ERROR_IRQ ST_STM32_I2C_V2_40005800_IRQ_ERROR
#define CONFIG_I2C_2_BITRATE ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY
#define CONFIG_I2C_3_BASE_ADDRESS ST_STM32_I2C_V2_40005C00_BASE_ADDRESS
#define CONFIG_I2C_3_EVENT_IRQ_PRI ST_STM32_I2C_V2_40005C00_IRQ_EVENT_PRIORITY
#define CONFIG_I2C_3_ERROR_IRQ_PRI ST_STM32_I2C_V2_40005C00_IRQ_ERROR_PRIORITY
#define CONFIG_I2C_3_NAME ST_STM32_I2C_V2_40005C00_LABEL
#define CONFIG_I2C_3_EVENT_IRQ ST_STM32_I2C_V2_40005C00_IRQ_EVENT
#define CONFIG_I2C_3_ERROR_IRQ ST_STM32_I2C_V2_40005C00_IRQ_ERROR
#define CONFIG_I2C_3_BITRATE ST_STM32_I2C_V2_40005C00_CLOCK_FREQUENCY
#define CONFIG_I2C_4_BASE_ADDRESS ST_STM32_I2C_V2_40008400_BASE_ADDRESS
#define CONFIG_I2C_4_EVENT_IRQ_PRI ST_STM32_I2C_V2_40008400_IRQ_EVENT_PRIORITY
#define CONFIG_I2C_4_ERROR_IRQ_PRI ST_STM32_I2C_V2_40008400_IRQ_ERROR_PRIORITY
#define CONFIG_I2C_4_NAME ST_STM32_I2C_V2_40008400_LABEL
#define CONFIG_I2C_4_EVENT_IRQ ST_STM32_I2C_V2_40008400_IRQ_EVENT
#define CONFIG_I2C_4_ERROR_IRQ ST_STM32_I2C_V2_40008400_IRQ_ERROR
#define CONFIG_I2C_4_BITRATE ST_STM32_I2C_V2_40008400_CLOCK_FREQUENCY
#define CONFIG_RTC_0_BASE_ADDRESS ST_STM32_RTC_40002800_BASE_ADDRESS
#define CONFIG_RTC_0_IRQ_PRI ST_STM32_RTC_40002800_IRQ_0_PRIORITY
#define CONFIG_RTC_0_IRQ ST_STM32_RTC_40002800_IRQ_0
#define CONFIG_RTC_0_NAME ST_STM32_RTC_40002800_LABEL
#define CONFIG_RTC_PRESCALER ST_STM32_RTC_40002800_PRESCALER
#define CONFIG_SPI_1_BASE_ADDRESS ST_STM32_SPI_FIFO_40013000_BASE_ADDRESS
#define CONFIG_SPI_1_IRQ_PRI ST_STM32_SPI_FIFO_40013000_IRQ_0_PRIORITY
#define CONFIG_SPI_1_NAME ST_STM32_SPI_FIFO_40013000_LABEL
#define CONFIG_SPI_1_IRQ ST_STM32_SPI_FIFO_40013000_IRQ_0
#define CONFIG_SPI_2_BASE_ADDRESS ST_STM32_SPI_FIFO_40003800_BASE_ADDRESS
#define CONFIG_SPI_2_IRQ_PRI ST_STM32_SPI_FIFO_40003800_IRQ_0_PRIORITY
#define CONFIG_SPI_2_NAME ST_STM32_SPI_FIFO_40003800_LABEL
#define CONFIG_SPI_2_IRQ ST_STM32_SPI_FIFO_40003800_IRQ_0
#define CONFIG_SPI_3_BASE_ADDRESS ST_STM32_SPI_FIFO_40003C00_BASE_ADDRESS
#define CONFIG_SPI_3_IRQ_PRI ST_STM32_SPI_FIFO_40003C00_IRQ_0_PRIORITY
#define CONFIG_SPI_3_NAME ST_STM32_SPI_FIFO_40003C00_LABEL
#define CONFIG_SPI_3_IRQ ST_STM32_SPI_FIFO_40003C00_IRQ_0
#define FLASH_DEV_BASE_ADDRESS ST_STM32L4_FLASH_CONTROLLER_40022000_BASE_ADDRESS
#define FLASH_DEV_NAME ST_STM32L4_FLASH_CONTROLLER_40022000_LABEL
#if defined(ST_STM32_USB_40006800_BASE_ADDRESS)
#define CONFIG_USB_BASE_ADDRESS ST_STM32_USB_40006800_BASE_ADDRESS
#define CONFIG_USB_IRQ ST_STM32_USB_40006800_IRQ_USB
#define CONFIG_USB_IRQ_PRI ST_STM32_USB_40006800_IRQ_USB_PRIORITY
#define CONFIG_USB_NUM_BIDIR_ENDPOINTS ST_STM32_USB_40006800_NUM_BIDIR_ENDPOINTS
#define CONFIG_USB_RAM_SIZE ST_STM32_USB_40006800_RAM_SIZE
#endif
#if defined(ST_STM32_OTGFS_50000000_BASE_ADDRESS)
#define CONFIG_USB_BASE_ADDRESS ST_STM32_OTGFS_50000000_BASE_ADDRESS
#define CONFIG_USB_IRQ ST_STM32_OTGFS_50000000_IRQ_OTGFS
#define CONFIG_USB_IRQ_PRI ST_STM32_OTGFS_50000000_IRQ_OTGFS_PRIORITY
#define CONFIG_USB_NUM_BIDIR_ENDPOINTS ST_STM32_OTGFS_50000000_NUM_BIDIR_ENDPOINTS
#define CONFIG_USB_RAM_SIZE ST_STM32_OTGFS_50000000_RAM_SIZE
#endif
#define CONFIG_PWM_STM32_1_DEV_NAME ST_STM32_PWM_40012C00_PWM_LABEL
#define CONFIG_PWM_STM32_1_PRESCALER ST_STM32_PWM_40012C00_PWM_ST_PRESCALER
#define CONFIG_PWM_STM32_2_DEV_NAME ST_STM32_PWM_40000000_PWM_LABEL
#define CONFIG_PWM_STM32_2_PRESCALER ST_STM32_PWM_40000000_PWM_ST_PRESCALER
#define CONFIG_PWM_STM32_3_DEV_NAME ST_STM32_PWM_40000400_PWM_LABEL
#define CONFIG_PWM_STM32_3_PRESCALER ST_STM32_PWM_40000400_PWM_ST_PRESCALER
#define CONFIG_PWM_STM32_4_DEV_NAME ST_STM32_PWM_40000800_PWM_LABEL
#define CONFIG_PWM_STM32_4_PRESCALER ST_STM32_PWM_40000800_PWM_ST_PRESCALER
#define CONFIG_PWM_STM32_5_DEV_NAME ST_STM32_PWM_40000C00_PWM_LABEL
#define CONFIG_PWM_STM32_5_PRESCALER ST_STM32_PWM_40000C00_PWM_ST_PRESCALER
#define CONFIG_PWM_STM32_6_DEV_NAME ST_STM32_PWM_40001000_PWM_LABEL
#define CONFIG_PWM_STM32_6_PRESCALER ST_STM32_PWM_40001000_PWM_ST_PRESCALER
#define CONFIG_PWM_STM32_7_DEV_NAME ST_STM32_PWM_40001400_PWM_LABEL
#define CONFIG_PWM_STM32_7_PRESCALER ST_STM32_PWM_40001400_PWM_ST_PRESCALER
#define CONFIG_PWM_STM32_8_DEV_NAME ST_STM32_PWM_40013400_PWM_LABEL
#define CONFIG_PWM_STM32_8_PRESCALER ST_STM32_PWM_40013400_PWM_ST_PRESCALER
#define CONFIG_PWM_STM32_15_DEV_NAME ST_STM32_PWM_40014000_PWM_LABEL
#define CONFIG_PWM_STM32_15_PRESCALER ST_STM32_PWM_40014000_PWM_ST_PRESCALER
#define CONFIG_PWM_STM32_16_DEV_NAME ST_STM32_PWM_40014400_PWM_LABEL
#define CONFIG_PWM_STM32_16_PRESCALER ST_STM32_PWM_40014400_PWM_ST_PRESCALER
#define CONFIG_PWM_STM32_17_DEV_NAME ST_STM32_PWM_40014800_PWM_LABEL
#define CONFIG_PWM_STM32_17_PRESCALER ST_STM32_PWM_40014800_PWM_ST_PRESCALER
#define CONFIG_CAN_1_BASE_ADDRESS ST_STM32_CAN_40006400_BASE_ADDRESS
#define CONFIG_CAN_1_BUS_SPEED ST_STM32_CAN_40006400_BUS_SPEED
#define CONFIG_CAN_1_NAME ST_STM32_CAN_40006400_LABEL
#define CONFIG_CAN_1_IRQ_TX ST_STM32_CAN_40006400_IRQ_TX
#define CONFIG_CAN_1_IRQ_RX0 ST_STM32_CAN_40006400_IRQ_RX0
#define CONFIG_CAN_1_IRQ_RX1 ST_STM32_CAN_40006400_IRQ_RX1
#define CONFIG_CAN_1_IRQ_SCE ST_STM32_CAN_40006400_IRQ_SCE
#define CONFIG_CAN_1_IRQ_PRIORITY ST_STM32_CAN_40006400_IRQ_0_PRIORITY
#define CONFIG_CAN_1_SJW ST_STM32_CAN_40006400_SJW
#define CONFIG_CAN_1_PROP_SEG_PHASE_SEG1 ST_STM32_CAN_40006400_PROP_SEG_PHASE_SEG1
#define CONFIG_CAN_1_PHASE_SEG2 ST_STM32_CAN_40006400_PHASE_SEG2
#define CONFIG_CAN_1_CLOCK_BUS ST_STM32_CAN_40006400_CLOCK_BUS
#define CONFIG_CAN_1_CLOCK_BITS ST_STM32_CAN_40006400_CLOCK_BITS
/* End of SoC Level DTS fixup file */

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/*
* Copyright (c) 2016 Open-RnD Sp. z o.o.
* Copyright (c) 2016 BayLibre, SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32L4X_FLASH_REGISTERS_H_
#define _STM32L4X_FLASH_REGISTERS_H_
enum {
STM32L4X_FLASH_LATENCY_0 = 0x0,
STM32L4X_FLASH_LATENCY_1 = 0x1,
STM32L4X_FLASH_LATENCY_2 = 0x2,
STM32L4X_FLASH_LATENCY_3 = 0x3,
STM32L4X_FLASH_LATENCY_4 = 0x4,
};
/* 3.7.1 FLASH_ACR */
union __ef_acr {
u32_t val;
struct {
u32_t latency :3 __packed;
u32_t rsvd__3_7 :5 __packed;
u32_t prften :1 __packed;
u32_t icen :1 __packed;
u32_t dcen :1 __packed;
u32_t icrst :1 __packed;
u32_t dcrst :1 __packed;
u32_t run_pd :1 __packed;
u32_t sleep_pd :1 __packed;
u32_t rsvd__16_31 :17 __packed;
} bit;
};
/* FLASH register map */
struct stm32l4x_flash {
volatile union __ef_acr acr;
volatile u32_t pdkeyr;
volatile u32_t keyr;
volatile u32_t optkeyr;
volatile u32_t sr;
volatile u32_t cr;
volatile u32_t eccr;
volatile u32_t rsvd_0;
volatile u32_t optr;
volatile u32_t pcrop1sr;
volatile u32_t pcrop1er;
volatile u32_t wrp1ar;
volatile u32_t wrp1br;
volatile u32_t rsvd_2[4];
/*
* The registers below are only present on STM32L4x2, STM32L4x5,
* STM32L4x6.
*/
volatile u32_t pcrop2sr;
volatile u32_t pcrop2er;
volatile u32_t wrp2ar;
volatile u32_t wrp2br;
};
#endif /* _STM32L4X_FLASH_REGISTERS_H_ */

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/* linker.ld - Linker command/script file */
/*
* Copyright (c) 2014-2016 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arch/arm/cortex_m/scripts/linker.ld>

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/*
* Copyright (c) 2016 Open-RnD Sp. z o.o.
* Copyright (c) 2016 BayLibre, SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief System/hardware module for STM32L4 processor
*/
#include <device.h>
#include <init.h>
#include <arch/cpu.h>
#include <cortex_m/exc.h>
/**
* @brief Perform basic hardware initialization at boot.
*
* This needs to be run from the very beginning.
* So the init priority has to be 0 (zero).
*
* @return 0
*/
static int stm32l4_init(struct device *arg)
{
u32_t key;
ARG_UNUSED(arg);
key = irq_lock();
_ClearFaults();
/* Install default handler that simply resets the CPU
* if configured in the kernel, NOP otherwise
*/
NMI_INIT();
irq_unlock(key);
/* Update CMSIS SystemCoreClock variable (HCLK) */
/* At reset, system core clock is set to 4 MHz from MSI */
SystemCoreClock = 4000000;
return 0;
}
SYS_INIT(stm32l4_init, PRE_KERNEL_1, 0);

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/*
* Copyright (c) 2016 Open-RnD Sp. z o.o.
* Copyright (c) 2016 BayLibre, SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file SoC configuration macros for the STM32L4 family processors.
*
* Based on reference manual:
* STM32L4x1, STM32L4x2, STM32L431xx STM32L443xx STM32L433xx, STM32L4x5,
* STM32l4x6 advanced ARM(r)-based 32-bit MCUs
*
* Chapter 2.2.2: Memory map and register boundary addresses
*/
#ifndef _STM32L4X_SOC_H_
#define _STM32L4X_SOC_H_
#ifndef _ASMLANGUAGE
#include <autoconf.h>
#include <stm32l4xx.h>
/* ARM CMSIS definitions must be included before kernel_includes.h.
* Therefore, it is essential to include kernel_includes.h after including
* core SOC-specific headers.
*/
#include <kernel_includes.h>
#define GPIO_REG_SIZE 0x400
/* base address for where GPIO registers start */
#define GPIO_PORTS_BASE (GPIOA_BASE)
#ifdef CONFIG_SERIAL_HAS_DRIVER
#include <stm32l4xx_ll_usart.h>
#include <stm32l4xx_ll_lpuart.h>
#endif
#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
#include <stm32l4xx_ll_utils.h>
#include <stm32l4xx_ll_bus.h>
#include <stm32l4xx_ll_rcc.h>
#include <stm32l4xx_ll_system.h>
#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
#ifdef CONFIG_SPI_STM32
#include <stm32l4xx_ll_spi.h>
#endif
#ifdef CONFIG_I2C
#include <stm32l4xx_ll_i2c.h>
#endif
#ifdef CONFIG_IWDG_STM32
#include <stm32l4xx_ll_iwdg.h>
#endif
#ifdef CONFIG_ENTROPY_STM32_RNG
#include <stm32l4xx_ll_rng.h>
#endif
#ifdef CONFIG_RTC_STM32
#include <stm32l4xx_ll_rtc.h>
#include <stm32l4xx_ll_exti.h>
#include <stm32l4xx_ll_pwr.h>
#endif
#ifdef CONFIG_USB
/* Required to remove USB transceiver supply isolation */
#include <stm32l4xx_ll_pwr.h>
#endif /* CONFIG_USB */
#endif /* !_ASMLANGUAGE */
#endif /* _STM32L4X_SOC_H_ */

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/*
* Copyright (c) 2016 Open-RnD Sp. z o.o.
* Copyright (c) 2016 BayLibre, SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief
*
* Based on reference manual:
* STM32L4x1, STM32L4x2, STM32L431xx STM32L443xx STM32L433xx, STM32L4x5,
* STM32l4x6 advanced ARM ® -based 32-bit MCUs
*
* General-purpose I/Os (GPIOs)
*/
#include <errno.h>
#include <device.h>
#include "soc.h"
#include "soc_registers.h"
#include <gpio.h>
#include <gpio/gpio_stm32.h>
enum {
STM32L4X_PIN3 = 3,
STM32L4X_PIN7 = 7,
STM32L4X_PIN11 = 11,
STM32L4X_PIN15 = 15,
};
#define STM32L4X_IDR_PIN_MASK 0x1
#define STM32L4X_AFR_MASK 0xf
/* GPIO registers - each GPIO port controls 16 pins */
struct stm32l4x_gpio {
u32_t moder;
u32_t otyper;
u32_t ospeedr;
u32_t pupdr;
u32_t idr;
u32_t odr;
u32_t bsrr;
u32_t lckr;
u32_t afr[2];
u32_t brr;
u32_t ascr; /* Only present on STM32L4x1, STM32L4x5, STM32L4x6 */
};
int stm32_gpio_flags_to_conf(int flags, int *pincfg)
{
int direction = flags & GPIO_DIR_MASK;
int pud = flags & GPIO_PUD_MASK;
if (!pincfg) {
return -EINVAL;
}
if (direction == GPIO_DIR_OUT) {
*pincfg = STM32_MODER_OUTPUT_MODE;
} else {
/* pull-{up,down} maybe? */
*pincfg = STM32_MODER_INPUT_MODE;
if (pud == GPIO_PUD_PULL_UP) {
*pincfg = *pincfg | STM32_PUPDR_PULL_UP;
} else if (pud == GPIO_PUD_PULL_DOWN) {
*pincfg = *pincfg | STM32_PUPDR_PULL_DOWN;
} else {
/* floating */
*pincfg = *pincfg | STM32_PUPDR_NO_PULL;
}
}
return 0;
}
int stm32_gpio_configure(u32_t *base_addr, int pin, int pinconf, int afnum)
{
volatile struct stm32l4x_gpio *gpio =
(struct stm32l4x_gpio *)(base_addr);
unsigned int mode, otype, ospeed, pupd;
unsigned int pin_shift = pin << 1;
unsigned int afr_bank = pin / 8;
unsigned int afr_shift = (pin % 8) << 2;
u32_t scratch;
mode = (pinconf >> STM32_MODER_SHIFT) & STM32_MODER_MASK;
otype = (pinconf >> STM32_OTYPER_SHIFT) & STM32_OTYPER_MASK;
ospeed = (pinconf >> STM32_OSPEEDR_SHIFT) & STM32_OSPEEDR_MASK;
pupd = (pinconf >> STM32_PUPDR_SHIFT) & STM32_PUPDR_MASK;
scratch = gpio->moder & ~(STM32_MODER_MASK << pin_shift);
gpio->moder = scratch | (mode << pin_shift);
scratch = gpio->ospeedr & ~(STM32_OSPEEDR_MASK << pin_shift);
gpio->ospeedr = scratch | (ospeed << pin_shift);
scratch = gpio->otyper & ~(STM32_OTYPER_MASK << pin);
gpio->otyper = scratch | (otype << pin);
scratch = gpio->pupdr & ~(STM32_PUPDR_MASK << pin_shift);
gpio->pupdr = scratch | (pupd << pin_shift);
scratch = gpio->afr[afr_bank] & ~(STM32_AFR_MASK << afr_shift);
gpio->afr[afr_bank] = scratch | (afnum << afr_shift);
return 0;
}
int stm32_gpio_set(u32_t *base, int pin, int value)
{
struct stm32l4x_gpio *gpio = (struct stm32l4x_gpio *)base;
int pval = 1 << (pin & 0xf);
if (value) {
gpio->odr |= pval;
} else {
gpio->odr &= ~pval;
}
return 0;
}
int stm32_gpio_get(u32_t *base, int pin)
{
struct stm32l4x_gpio *gpio = (struct stm32l4x_gpio *)base;
return (gpio->idr >> pin) & STM32L4X_IDR_PIN_MASK;
}
int stm32_gpio_enable_int(int port, int pin)
{
struct stm32l4x_syscfg *syscfg = (struct stm32l4x_syscfg *)SYSCFG_BASE;
struct device *clk = device_get_binding(STM32_CLOCK_CONTROL_NAME);
u32_t *reg;
/* Enable SYSCFG clock */
struct stm32_pclken pclken = {
.bus = STM32_CLOCK_BUS_APB2,
.enr = LL_APB2_GRP1_PERIPH_SYSCFG
};
clock_control_on(clk, (clock_control_subsys_t *) &pclken);
if (pin <= STM32L4X_PIN3) {
reg = &syscfg->exticr1;
} else if (pin <= STM32L4X_PIN7) {
reg = &syscfg->exticr2;
} else if (pin <= STM32L4X_PIN11) {
reg = &syscfg->exticr3;
} else if (pin <= STM32L4X_PIN15) {
reg = &syscfg->exticr4;
} else {
return -EINVAL;
}
*reg &= ~(STM32L4X_SYSCFG_EXTICR_PIN_MASK << ((pin % 4) * 4));
*reg |= port << ((pin % 4) * 4);
return 0; /* Nothing to do here for STM32L4s */
}

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/*
* Copyright (c) 2016 Open-RnD Sp. z o.o.
* Copyright (c) 2016 BayLibre, SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32L4X_SOC_REGISTERS_H_
#define _STM32L4X_SOC_REGISTERS_H_
/* include register mapping headers */
#include "flash_registers.h"
#include "syscfg_registers.h"
#endif /* _STM32L4X_SOC_REGISTERS_H_ */

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/*
* Copyright (c) 2016 BayLibre, SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32L4X_SYSCFG_REGISTERS_H_
#define _STM32L4X_SYSCFG_REGISTERS_H_
#define STM32L4X_SYSCFG_EXTICR_PIN_MASK 7
/* SYSCFG registers */
struct stm32l4x_syscfg {
u32_t memrmp;
u32_t cfgr1;
u32_t exticr1;
u32_t exticr2;
u32_t exticr3;
u32_t exticr4;
u32_t scsr;
u32_t cfgr2;
u32_t swpr;
u32_t skr;
};
#endif /* _STM32L4X_SYSCFG_REGISTERS_H_ */