arm: soc: move arm SoCs to top-dir

Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>

soc/arm/st_stm32/CMakeLists.txt

@@ -0,0 +1,2 @@
+add_subdirectory(${SOC_SERIES})
+add_subdirectory(common)

soc/arm/st_stm32/Kconfig

@@ -0,0 +1,30 @@
+# Kconfig - ST Microelectronics STM32 MCU line
+#
+# Copyright (c) 2016 Open-RnD Sp. z o.o.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config SOC_FAMILY_STM32
+	bool
+	# omit prompt to signify a "hidden" option
+	select HAS_SEGGER_RTT
+	select HAS_DTS_I2C_DEVICE if I2C
+	select HAS_DTS_SPI_DEVICE if SPI
+
+if SOC_FAMILY_STM32
+
+config SOC_FAMILY
+	string
+	default "st_stm32"
+
+config STM32_ARM_MPU_ENABLE
+	bool "Enable MPU on STM32"
+	depends on CPU_HAS_MPU
+	select ARM_MPU
+	help
+	  Enable MPU support on STM32 SoCs
+
+source "soc/arm/st_stm32/*/Kconfig.soc"
+
+endif # SOC_FAMILY_STM32

soc/arm/st_stm32/Kconfig.defconfig

@@ -0,0 +1 @@
+source "soc/arm/st_stm32/*/Kconfig.defconfig.series"

soc/arm/st_stm32/Kconfig.soc

@@ -0,0 +1,8 @@
+# Kconfig - ST Microelectronics STM32 MCU line
+#
+# Copyright (c) 2016 Open-RnD Sp. z o.o.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+source "soc/arm/st_stm32/*/Kconfig.series"

soc/arm/st_stm32/common/CMakeLists.txt

@@ -0,0 +1,2 @@
+zephyr_sources_ifdef(CONFIG_STM32_ARM_MPU_ENABLE arm_mpu_regions.c)
+zephyr_sources(stm32cube_hal.c)

soc/arm/st_stm32/common/Kconfig.defconfig.series

@@ -0,0 +1,75 @@
+# Kconfig.defconfig.series - ST Microelectronics STM32 all MCU lines
+#
+# Copyright (c) 2017, I-SENSE group of ICCS
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_FAMILY_STM32
+
+if SERIAL
+
+config UART_STM32
+	def_bool y
+
+endif #SERIAL
+
+if GPIO
+
+config GPIO_STM32
+	def_bool y
+
+config GPIO_STM32_PORTA
+	def_bool y
+
+config GPIO_STM32_PORTB
+	def_bool y
+
+config GPIO_STM32_PORTC
+	def_bool y
+
+endif #GPIO
+
+if PINMUX
+
+config PINMUX_STM32
+	def_bool y
+
+endif #PINMUX
+
+if WATCHDOG
+
+config IWDG_STM32
+	def_bool y
+
+endif # WATCHDOG
+
+if PWM
+
+config PWM_STM32
+	def_bool y
+
+endif # PWM
+
+if SPI
+
+config SPI_STM32
+	def_bool y
+
+endif # SPI
+
+if I2C
+
+config I2C_STM32
+	def_bool y
+
+endif
+
+if USB
+
+config USB_DC_STM32
+	def_bool y
+
+endif # USB
+
+endif # SOC_FAMILY_STM32

soc/arm/st_stm32/common/arm_mpu_mem_cfg.h

@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2017 Linaro Limited.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _ARM_MPU_MEM_CFG_H_
+#define _ARM_MPU_MEM_CFG_H_
+
+#include <soc.h>
+#include <arch/arm/cortex_m/mpu/arm_mpu.h>
+
+/* Flash Region Definitions */
+#if CONFIG_FLASH_SIZE == 64
+#define REGION_FLASH_SIZE REGION_64K
+#elif CONFIG_FLASH_SIZE == 128
+#define REGION_FLASH_SIZE REGION_128K
+#elif CONFIG_FLASH_SIZE == 256
+#define REGION_FLASH_SIZE REGION_256K
+#elif CONFIG_FLASH_SIZE == 512
+#define REGION_FLASH_SIZE REGION_512K
+#elif CONFIG_FLASH_SIZE == 1024
+#define REGION_FLASH_SIZE REGION_1M
+#elif CONFIG_FLASH_SIZE == 1536
+#define REGION_FLASH_SIZE REGION_2M	/* last 512kB are not mapped */
+#elif CONFIG_FLASH_SIZE == 2048
+#define REGION_FLASH_SIZE REGION_2M
+#else
+#error "Unsupported configuration"
+#endif
+
+/* SRAM Region Definitions */
+#if CONFIG_SRAM_SIZE == 12
+#define REGION_SRAM_0_SIZE REGION_8K
+#define REGION_SRAM_1_START 0x2000
+#define REGION_SRAM_1_SIZE REGION_4K
+#elif CONFIG_SRAM_SIZE == 20
+#define REGION_SRAM_0_SIZE REGION_16K
+#define REGION_SRAM_1_START 0x4000
+#define REGION_SRAM_1_SIZE REGION_4K
+#elif CONFIG_SRAM_SIZE == 32
+#define REGION_SRAM_0_SIZE REGION_16K
+#define REGION_SRAM_1_START 0x4000
+#define REGION_SRAM_1_SIZE REGION_16K
+#elif CONFIG_SRAM_SIZE == 40
+#define REGION_SRAM_0_SIZE REGION_32K
+#define REGION_SRAM_1_START 0x8000
+#define REGION_SRAM_1_SIZE REGION_8K
+#elif CONFIG_SRAM_SIZE == 64
+#define REGION_SRAM_0_SIZE REGION_32K
+#define REGION_SRAM_1_START 0x8000
+#define REGION_SRAM_1_SIZE REGION_32K
+#elif CONFIG_SRAM_SIZE == 96
+#define REGION_SRAM_0_SIZE REGION_64K
+#define REGION_SRAM_1_START 0x10000
+#define REGION_SRAM_1_SIZE REGION_32K
+#elif CONFIG_SRAM_SIZE == 128
+#define REGION_SRAM_0_SIZE REGION_64K
+#define REGION_SRAM_1_START 0x10000
+#define REGION_SRAM_1_SIZE REGION_64K
+#elif CONFIG_SRAM_SIZE == 192
+#define REGION_SRAM_0_SIZE REGION_128K
+#define REGION_SRAM_1_START 0x20000
+#define REGION_SRAM_1_SIZE REGION_64K
+#elif CONFIG_SRAM_SIZE == 256
+#define REGION_SRAM_0_SIZE REGION_128K
+#define REGION_SRAM_1_START 0x20000
+#define REGION_SRAM_1_SIZE REGION_128K
+#elif CONFIG_SRAM_SIZE == 320
+#define REGION_SRAM_0_SIZE REGION_256K
+#define REGION_SRAM_1_START 0x40000
+#define REGION_SRAM_1_SIZE REGION_64K
+#elif CONFIG_SRAM_SIZE == 384
+#define REGION_SRAM_0_SIZE REGION_256K
+#define REGION_SRAM_1_START 0x40000
+#define REGION_SRAM_1_SIZE REGION_128K
+#else
+#error "Unsupported configuration"
+#endif
+
+#endif /* _ARM_MPU_MEM_CFG_H_ */

soc/arm/st_stm32/common/arm_mpu_regions.c

@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2017 Linaro Limited.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <soc.h>
+#include <arch/arm/cortex_m/mpu/arm_mpu.h>
+
+#include "arm_mpu_mem_cfg.h"
+
+/* SoC Private Peripheral Bus */
+#define PPB_BASE  0xE0000000
+
+static struct arm_mpu_region mpu_regions[] = {
+	/* Region 0 */
+	MPU_REGION_ENTRY("FLASH_0",
+			 CONFIG_FLASH_BASE_ADDRESS,
+			 REGION_FLASH_ATTR(REGION_FLASH_SIZE)),
+	/* Region 1 */
+	MPU_REGION_ENTRY("RAM_0",
+			 CONFIG_SRAM_BASE_ADDRESS,
+			 REGION_RAM_ATTR(REGION_SRAM_0_SIZE)),
+	/* Region 2 */
+	MPU_REGION_ENTRY("RAM_1",
+			 (CONFIG_SRAM_BASE_ADDRESS + REGION_SRAM_1_START),
+			 REGION_RAM_ATTR(REGION_SRAM_1_SIZE)),
+};
+
+struct arm_mpu_config mpu_config = {
+	.num_regions = ARRAY_SIZE(mpu_regions),
+	.mpu_regions = mpu_regions,
+};

soc/arm/st_stm32/common/stm32cube_hal.c

@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2018, I-SENSE group of ICCS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Zephyr's implementation for STM32Cube HAL core initialization
+ *        functions. These functions are declared as __weak in
+ *        STM32Cube HAL in order to be overwritten in case of other
+ *        implementations.
+ */
+
+#include <kernel.h>
+#include <soc.h>
+/**
+ * @brief This function configures the source of stm32cube time base.
+ *        Cube HAL expects a 1ms tick which matches with k_uptime_get_32.
+ *        Tick interrupt priority is not used
+ * @return HAL status
+ */
+uint32_t HAL_GetTick(void)
+{
+	return k_uptime_get_32();
+}
+
+/**
+ * @brief This function provides minimum delay (in milliseconds) based
+ *	  on variable incremented.
+ * @param Delay: specifies the delay time length, in milliseconds.
+ * @return None
+ */
+void HAL_Delay(__IO uint32_t Delay)
+{
+	k_sleep(Delay);
+}

soc/arm/st_stm32/stm32f0/CMakeLists.txt

@@ -0,0 +1,3 @@
+zephyr_include_directories(${ZEPHYR_BASE}/drivers)
+zephyr_sources(soc.c)
+zephyr_sources_ifdef(CONFIG_GPIO soc_gpio.c)

soc/arm/st_stm32/stm32f0/Kconfig.defconfig.series

@@ -0,0 +1,32 @@
+# Kconfig - ST Microelectronics STM32F0 MCU line
+#
+# Copyright (c) 2017 RnDity Sp. z o.o.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_SERIES_STM32F0X
+
+source "soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f0*"
+
+config SOC_SERIES
+	default "stm32f0"
+
+if GPIO_STM32
+
+config GPIO_STM32_PORTD
+	default y
+
+config GPIO_STM32_PORTF
+	default y
+
+endif # GPIO_STM32
+
+if I2C_STM32
+
+config I2C_STM32_V2
+	def_bool y
+
+endif # I2C_STM32
+
+endif # SOC_SERIES_STM32F0X

soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f030x8

@@ -0,0 +1,18 @@
+# Kconfig - ST Microelectronics STM32F030X8 MCU
+#
+# Copyright (c) 2017 RnDity Sp. z o.o.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_STM32F030X8
+
+config SOC
+	string
+	default "stm32f030x8"
+
+config NUM_IRQS
+	int
+	default 29
+
+endif # SOC_STM32F030X8

soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f051x8

@@ -0,0 +1,18 @@
+# Kconfig - ST Microelectronics STM32F051X8 MCU
+#
+# Copyright (c) 2018 Nathan Tsoi
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_STM32F051X8
+
+config SOC
+	string
+	default "stm32f051x8"
+
+config NUM_IRQS
+	int
+	default 31
+
+endif # SOC_STM32F051X8

soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f070xb

@@ -0,0 +1,18 @@
+# Kconfig - ST Microelectronics STM32F070XB MCU
+#
+# Copyright (c) 2018 qianfan Zhao
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_STM32F070XB
+
+config SOC
+	string
+	default "stm32f070xb"
+
+config NUM_IRQS
+	int
+	default 32
+
+endif # SOC_STM32F070XB

soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f072xb

@@ -0,0 +1,18 @@
+# Kconfig - ST Microelectronics STM32F072XB MCU
+#
+# Copyright (c) 2017 BayLibre, SAS
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_STM32F072XB
+
+config SOC
+	string
+	default "stm32f072xb"
+
+config NUM_IRQS
+	int
+	default 32
+
+endif # SOC_STM32F072XB

soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f091xc

@@ -0,0 +1,18 @@
+# Kconfig - ST Microelectronics STM32F091XC MCU
+#
+# Copyright (c) 2017 b0661n0e17e@gmail.com
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_STM32F091XC
+
+config SOC
+	string
+	default "stm32f091xc"
+
+config NUM_IRQS
+	int
+	default 31
+
+endif # SOC_STM32F091XC

soc/arm/st_stm32/stm32f0/Kconfig.series

@@ -0,0 +1,18 @@
+# Kconfig - ST Microelectronics STM32F0 MCU series
+#
+# Copyright (c) 2017 RnDity Sp. z o.o.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config SOC_SERIES_STM32F0X
+	bool "STM32F0x Series MCU"
+	select CPU_CORTEX_M0
+	select CPU_CORTEX_M0_HAS_VECTOR_TABLE_REMAP
+	select SOC_FAMILY_STM32
+	select SYS_POWER_LOW_POWER_STATE_SUPPORTED
+	select CPU_HAS_SYSTICK
+	select HAS_STM32CUBE
+	select CLOCK_CONTROL_STM32_CUBE if CLOCK_CONTROL
+	help
+	 Enable support for STM32F0 MCU series

soc/arm/st_stm32/stm32f0/Kconfig.soc

@@ -0,0 +1,27 @@
+# Kconfig - ST Microelectronics STM32F0 MCU line
+#
+# Copyright (c) 2017 RnDity Sp. z o.o.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+choice
+prompt "STM32F0x MCU Selection"
+depends on SOC_SERIES_STM32F0X
+
+config SOC_STM32F030X8
+	bool "STM32F030X8"
+
+config SOC_STM32F051X8
+	bool "STM32F051X8"
+
+config SOC_STM32F070XB
+	bool "STM32F070XB"
+
+config SOC_STM32F072XB
+	bool "STM32F072XB"
+
+config SOC_STM32F091XC
+	bool "STM32F091XC"
+
+endchoice

soc/arm/st_stm32/stm32f0/dts.fixup

@@ -0,0 +1,86 @@
+/* SoC level DTS fixup file */
+
+#define CONFIG_NUM_IRQ_PRIO_BITS	        ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
+
+#define CONFIG_UART_STM32_USART_1_BASE_ADDRESS	ST_STM32_USART_40013800_BASE_ADDRESS
+#define CONFIG_UART_STM32_USART_1_BAUD_RATE	ST_STM32_USART_40013800_CURRENT_SPEED
+#define CONFIG_UART_STM32_USART_1_IRQ_PRI	ST_STM32_USART_40013800_IRQ_0_PRIORITY
+#define CONFIG_UART_STM32_USART_1_NAME		ST_STM32_USART_40013800_LABEL
+#define USART_1_IRQ				ST_STM32_USART_40013800_IRQ_0
+
+#define CONFIG_UART_STM32_USART_2_BASE_ADDRESS	ST_STM32_USART_40004400_BASE_ADDRESS
+#define CONFIG_UART_STM32_USART_2_BAUD_RATE	ST_STM32_USART_40004400_CURRENT_SPEED
+#define CONFIG_UART_STM32_USART_2_IRQ_PRI	ST_STM32_USART_40004400_IRQ_0_PRIORITY
+#define CONFIG_UART_STM32_USART_2_NAME		ST_STM32_USART_40004400_LABEL
+#define USART_2_IRQ				ST_STM32_USART_40004400_IRQ_0
+
+#define CONFIG_I2C_1_BASE_ADDRESS		ST_STM32_I2C_V2_40005400_BASE_ADDRESS
+#define CONFIG_I2C_1_COMBINED_IRQ_PRI		ST_STM32_I2C_V2_40005400_IRQ_COMBINED_PRIORITY
+#define CONFIG_I2C_1_NAME			ST_STM32_I2C_V2_40005400_LABEL
+#define CONFIG_I2C_1_COMBINED_IRQ		ST_STM32_I2C_V2_40005400_IRQ_COMBINED
+#define CONFIG_I2C_1_BITRATE			ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY
+
+#define CONFIG_I2C_2_BASE_ADDRESS		ST_STM32_I2C_V2_40005800_BASE_ADDRESS
+#define CONFIG_I2C_2_COMBINED_IRQ_PRI		ST_STM32_I2C_V2_40005800_IRQ_COMBINED_PRIORITY
+#define CONFIG_I2C_2_NAME			ST_STM32_I2C_V2_40005800_LABEL
+#define CONFIG_I2C_2_COMBINED_IRQ		ST_STM32_I2C_V2_40005800_IRQ_COMBINED
+#define CONFIG_I2C_2_BITRATE			ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY
+
+#define CONFIG_SPI_1_BASE_ADDRESS		ST_STM32_SPI_FIFO_40013000_BASE_ADDRESS
+#define CONFIG_SPI_1_IRQ_PRI			ST_STM32_SPI_FIFO_40013000_IRQ_0_PRIORITY
+#define CONFIG_SPI_1_NAME			ST_STM32_SPI_FIFO_40013000_LABEL
+#define CONFIG_SPI_1_IRQ			ST_STM32_SPI_FIFO_40013000_IRQ_0
+
+#define CONFIG_SPI_2_BASE_ADDRESS		ST_STM32_SPI_FIFO_40003800_BASE_ADDRESS
+#define CONFIG_SPI_2_IRQ_PRI			ST_STM32_SPI_FIFO_40003800_IRQ_0_PRIORITY
+#define CONFIG_SPI_2_NAME			ST_STM32_SPI_FIFO_40003800_LABEL
+#define CONFIG_SPI_2_IRQ			ST_STM32_SPI_FIFO_40003800_IRQ_0
+
+#define CONFIG_CAN_1_BASE_ADDRESS		ST_STM32_CAN_40006400_BASE_ADDRESS
+#define CONFIG_CAN_1_BUS_SPEED			ST_STM32_CAN_40006400_BUS_SPEED
+#define CONFIG_CAN_1_NAME			ST_STM32_CAN_40006400_LABEL
+#define CONFIG_CAN_1_IRQ			ST_STM32_CAN_40006400_IRQ_0
+#define CONFIG_CAN_1_IRQ_PRIORITY		ST_STM32_CAN_40006400_IRQ_0_PRIORITY
+#define CONFIG_CAN_1_SJW			ST_STM32_CAN_40006400_SJW
+#define CONFIG_CAN_1_PROP_SEG_PHASE_SEG1	ST_STM32_CAN_40006400_PROP_SEG_PHASE_SEG1
+#define CONFIG_CAN_1_PHASE_SEG2			ST_STM32_CAN_40006400_PHASE_SEG2
+#define CONFIG_CAN_1_CLOCK_BUS			ST_STM32_CAN_40006400_CLOCK_BUS
+#define CONFIG_CAN_1_CLOCK_BITS			ST_STM32_CAN_40006400_CLOCK_BITS
+
+#define FLASH_DEV_BASE_ADDRESS		        ST_STM32F0_FLASH_CONTROLLER_40022000_BASE_ADDRESS
+#define FLASH_DEV_NAME			        ST_STM32F0_FLASH_CONTROLLER_40022000_LABEL
+
+#define CONFIG_USB_BASE_ADDRESS		ST_STM32_USB_40005C00_BASE_ADDRESS
+#define CONFIG_USB_IRQ				ST_STM32_USB_40005C00_IRQ_USB
+#define CONFIG_USB_IRQ_PRI			ST_STM32_USB_40005C00_IRQ_USB_PRIORITY
+#define CONFIG_USB_NUM_BIDIR_ENDPOINTS		ST_STM32_USB_40005C00_NUM_BIDIR_ENDPOINTS
+#define CONFIG_USB_RAM_SIZE			ST_STM32_USB_40005C00_RAM_SIZE
+
+#define CONFIG_PWM_STM32_1_DEV_NAME             ST_STM32_PWM_40012C00_PWM_LABEL
+#define CONFIG_PWM_STM32_1_PRESCALER            ST_STM32_PWM_40012C00_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_2_DEV_NAME             ST_STM32_PWM_40000000_PWM_LABEL
+#define CONFIG_PWM_STM32_2_PRESCALER            ST_STM32_PWM_40000000_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_3_DEV_NAME             ST_STM32_PWM_40000400_PWM_LABEL
+#define CONFIG_PWM_STM32_3_PRESCALER            ST_STM32_PWM_40000400_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_6_DEV_NAME             ST_STM32_PWM_40001000_PWM_LABEL
+#define CONFIG_PWM_STM32_6_PRESCALER            ST_STM32_PWM_40001000_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_7_DEV_NAME             ST_STM32_PWM_40001400_PWM_LABEL
+#define CONFIG_PWM_STM32_7_PRESCALER            ST_STM32_PWM_40001400_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_14_DEV_NAME            ST_STM32_PWM_40002000_PWM_LABEL
+#define CONFIG_PWM_STM32_14_PRESCALER           ST_STM32_PWM_40002000_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_15_DEV_NAME            ST_STM32_PWM_40014000_PWM_LABEL
+#define CONFIG_PWM_STM32_15_PRESCALER           ST_STM32_PWM_40014000_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_16_DEV_NAME            ST_STM32_PWM_40014400_PWM_LABEL
+#define CONFIG_PWM_STM32_16_PRESCALER           ST_STM32_PWM_40014400_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_17_DEV_NAME            ST_STM32_PWM_40014800_PWM_LABEL
+#define CONFIG_PWM_STM32_17_PRESCALER           ST_STM32_PWM_40014800_PWM_ST_PRESCALER
+
+/* End of SoC Level DTS fixup file */

soc/arm/st_stm32/stm32f0/flash_registers.h

@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2017 RnDity Sp. z o.o.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _STM32F0X_FLASH_REGISTERS_H_
+#define _STM32F0X_FLASH_REGISTERS_H_
+
+#include <zephyr/types.h>
+
+/**
+ * @brief
+ *
+ * Based on reference manual:
+ *   STM32F030x4/x6/x8/xC,
+ *   STM32F070x6/xB advanced ARM ® -based MCUs
+ *
+ * Chapter 3.3.5: Embedded Flash Memory
+ */
+
+enum {
+	STM32_FLASH_LATENCY_0 = 0x0,
+	STM32_FLASH_LATENCY_1 = 0x1
+};
+
+/* 3.3.5.1 FLASH_ACR */
+union ef_acr {
+	u32_t val;
+	struct {
+		u32_t latency :3 __packed;
+		u32_t rsvd__3 :1 __packed;
+		u32_t prftbe :1 __packed;
+		u32_t prftbs :1 __packed;
+		u32_t rsvd__6_31 :26 __packed;
+	} bit;
+};
+
+/* 3.3.5 Embedded flash registers */
+struct stm32f0x_flash {
+	volatile union ef_acr acr;
+	volatile u32_t keyr;
+	volatile u32_t optkeyr;
+	volatile u32_t sr;
+	volatile u32_t cr;
+	volatile u32_t ar;
+	volatile u32_t rsvd;
+	volatile u32_t obr;
+	volatile u32_t wrpr;
+};
+
+#endif /* _STM32F0X_FLASH_REGISTERS_H_ */

soc/arm/st_stm32/stm32f0/gpio_registers.h

@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2017 RnDity Sp. z o.o.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _STM32F0X_GPIO_REGISTERS_H_
+#define _STM32F0X_GPIO_REGISTERS_H_
+
+/**
+ * @brief
+ *
+ * Based on reference manual:
+ *   STM32F030x4/x6/x8/xC,
+ *   STM32F070x6/xB advanced ARM ® -based MCUs
+ *
+ * Chapter 8: General-purpose I/Os (GPIO)
+ * Chapter 9: System configuration controller (SYSCFG)
+ */
+
+struct stm32f0x_gpio {
+	u32_t moder;
+	u32_t otyper;
+	u32_t ospeedr;
+	u32_t pupdr;
+	u32_t idr;
+	u32_t odr;
+	u32_t bsrr;
+	u32_t lckr;
+	u32_t afr[2];
+	u32_t brr;
+};
+
+union syscfg_cfgr1 {
+	u32_t val;
+	struct {
+		u32_t mem_mode :2 __packed;
+		u32_t rsvd__2_7 :6 __packed;
+		u32_t adc_dma_rmp :1 __packed;
+		u32_t usart1_tx_dma_rmp :1 __packed;
+		u32_t usart1_rx_dma_rmp :1 __packed;
+		u32_t tim16_dma_rmp :1 __packed;
+		u32_t tim17_dma_rmp :1 __packed;
+		u32_t rsvd__13_15 :3 __packed;
+		u32_t i2c_pb6_fmp :1 __packed;
+		u32_t i2c_pb7_fmp :1 __packed;
+		u32_t i2c_pb8_fmp :1 __packed;
+		u32_t i2c_pb9_fmp :1 __packed;
+		u32_t i2c1_fmp :1 __packed;
+		u32_t rsvd__21 :1 __packed;
+		u32_t i2c_pa9_fmp :1 __packed;
+		u32_t i2c_pa10_fmp :1 __packed;
+		u32_t rsvd__24_25 :2 __packed;
+		u32_t usart3_dma_rmp :1 __packed;
+		u32_t rsvd__27_31 :5 __packed;
+	} bit;
+};
+
+union syscfg__exticr {
+	u32_t val;
+	struct {
+		u16_t exti;
+		u16_t rsvd__16_31;
+	} bit;
+};
+
+struct stm32f0x_syscfg {
+	union syscfg_cfgr1 cfgr1;
+	u32_t rsvd;
+	union syscfg__exticr exticr1;
+	union syscfg__exticr exticr2;
+	union syscfg__exticr exticr3;
+	union syscfg__exticr exticr4;
+	u32_t cfgr2;
+};
+
+#endif /* _STM32F0X_GPIO_REGISTERS_H_ */

soc/arm/st_stm32/stm32f0/linker.ld

@@ -0,0 +1,9 @@
+/* linker.ld - Linker command/script file */
+
+/*
+ * Copyright (c) 2014-2016 Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arch/arm/cortex_m/scripts/linker.ld>

soc/arm/st_stm32/stm32f0/soc.c

@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2017 RnDity Sp. z o.o.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for STM32F0 processor
+ */
+
+#include <device.h>
+#include <init.h>
+#include <arch/cpu.h>
+#include <cortex_m/exc.h>
+#include <linker/linker-defs.h>
+#include <string.h>
+
+
+/**
+ * @brief Relocate vector table to SRAM.
+ *
+ * On Cortex-M0 platforms, the Vector Base address cannot be changed.
+ *
+ * A Zephyr image that is run from the mcuboot bootloader must relocate the
+ * vector table to SRAM to be able to replace the vectors pointing to the
+ * bootloader.
+ *
+ * A zephyr image that is a bootloader does not have to relocate the
+ * vector table.
+ *
+ * Replaces the default function from prep_c.c.
+ *
+ * @note Zephyr applications that will not be loaded by a bootloader should
+ *       pretend to be a bootloader if the SRAM vector table is not needed.
+ */
+void relocate_vector_table(void)
+{
+#ifndef CONFIG_IS_BOOTLOADER
+	extern char _ram_vector_start[];
+
+	size_t vector_size = (size_t)_vector_end - (size_t)_vector_start;
+
+	memcpy(_ram_vector_start, _vector_start, vector_size);
+	LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_SRAM);
+#endif
+}
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ * So the init priority has to be 0 (zero).
+ *
+ * @return 0
+ */
+static int stm32f0_init(struct device *arg)
+{
+	u32_t key;
+
+	ARG_UNUSED(arg);
+
+	key = irq_lock();
+
+	_ClearFaults();
+
+	/* Install default handler that simply resets the CPU
+	 * if configured in the kernel, NOP otherwise
+	 */
+	NMI_INIT();
+
+	irq_unlock(key);
+
+	/* Update CMSIS SystemCoreClock variable (HCLK) */
+	/* At reset, system core clock is set to 8 MHz from HSI */
+	SystemCoreClock = 8000000;
+
+	return 0;
+}
+
+SYS_INIT(stm32f0_init, PRE_KERNEL_1, 0);

soc/arm/st_stm32/stm32f0/soc.h

@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2017 RnDity Sp. z o.o.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file SoC configuration macros for the STM32F0 family processors.
+ *
+ * Based on reference manual:
+ *   STM32F030x4/x6/x8/xC,
+ *   STM32F070x6/xB advanced ARM ® -based MCUs
+ *
+ * Chapter 2.2: Memory organization
+ */
+
+
+#ifndef _STM32F0_SOC_H_
+#define _STM32F0_SOC_H_
+
+#define GPIO_REG_SIZE         0x400
+/* base address for where GPIO registers start */
+#define GPIO_PORTS_BASE       (GPIOA_BASE)
+
+#ifndef _ASMLANGUAGE
+
+#include <stm32f0xx.h>
+
+/* ARM CMSIS definitions must be included before kernel_includes.h.
+ * Therefore, it is essential to include kernel_includes.h after including
+ * core SOC-specific headers.
+ */
+#include <kernel_includes.h>
+
+#ifdef CONFIG_SERIAL_HAS_DRIVER
+#include <stm32f0xx_ll_usart.h>
+#endif
+
+#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
+#include <stm32f0xx_ll_utils.h>
+#include <stm32f0xx_ll_bus.h>
+#include <stm32f0xx_ll_rcc.h>
+#include <stm32f0xx_ll_system.h>
+#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
+
+#ifdef CONFIG_IWDG_STM32
+#include <stm32f0xx_ll_iwdg.h>
+#endif
+
+#ifdef CONFIG_I2C_STM32_V2
+#include <stm32f0xx_ll_i2c.h>
+#endif
+
+#ifdef CONFIG_SPI_STM32
+#include <stm32f0xx_ll_spi.h>
+#endif
+
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _STM32F0_SOC_H_ */

soc/arm/st_stm32/stm32f0/soc_gpio.c

@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2017 RnDity Sp. z o.o.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @brief
+ *
+ * Based on reference manual:
+ *   STM32F030x4/x6/x8/xC,
+ *   STM32F070x6/xB advanced ARM ® -based MCUs
+ *
+ * Chapter 8: General-purpose I/Os (GPIO)
+ */
+
+#include <errno.h>
+
+#include <device.h>
+#include "soc.h"
+#include "soc_registers.h"
+#include <gpio.h>
+#include <gpio/gpio_stm32.h>
+
+int stm32_gpio_flags_to_conf(int flags, int *pincfg)
+{
+	int direction = flags & GPIO_DIR_MASK;
+	int pud = flags & GPIO_PUD_MASK;
+
+	if (!pincfg) {
+		return -EINVAL;
+	}
+
+	if (direction == GPIO_DIR_OUT) {
+		*pincfg = STM32_MODER_OUTPUT_MODE;
+	} else {
+		/* pull-{up,down} maybe? */
+		*pincfg = STM32_MODER_INPUT_MODE;
+		if (pud == GPIO_PUD_PULL_UP) {
+			*pincfg = *pincfg | STM32_PUPDR_PULL_UP;
+		} else if (pud == GPIO_PUD_PULL_DOWN) {
+			*pincfg = *pincfg | STM32_PUPDR_PULL_DOWN;
+		} else {
+			/* floating */
+			*pincfg = *pincfg | STM32_PUPDR_NO_PULL;
+		}
+	}
+
+	return 0;
+}
+
+int stm32_gpio_configure(u32_t *base_addr, int pin, int conf, int altf)
+{
+	volatile struct stm32f0x_gpio *gpio =
+		(struct stm32f0x_gpio *)(base_addr);
+	unsigned int mode, otype, ospeed, pupd;
+	unsigned int pin_shift = pin << 1;
+	unsigned int afr_bank = pin / 8;
+	unsigned int afr_shift = (pin % 8) << 2;
+	u32_t scratch;
+
+	mode = (conf >> STM32_MODER_SHIFT) & STM32_MODER_MASK;
+	otype = (conf >> STM32_OTYPER_SHIFT) & STM32_OTYPER_MASK;
+	ospeed = (conf >> STM32_OSPEEDR_SHIFT) & STM32_OSPEEDR_MASK;
+	pupd = (conf >> STM32_PUPDR_SHIFT) & STM32_PUPDR_MASK;
+
+	scratch = gpio->moder & ~(STM32_MODER_MASK << pin_shift);
+	gpio->moder = scratch | (mode << pin_shift);
+
+	scratch = gpio->ospeedr & ~(STM32_OSPEEDR_MASK << pin_shift);
+	gpio->ospeedr = scratch | (ospeed << pin_shift);
+
+	scratch = gpio->otyper & ~(STM32_OTYPER_MASK << pin);
+	gpio->otyper = scratch | (otype << pin);
+
+	scratch = gpio->pupdr & ~(STM32_PUPDR_MASK << pin_shift);
+	gpio->pupdr = scratch | (pupd << pin_shift);
+
+	scratch = gpio->afr[afr_bank] & ~(STM32_AFR_MASK << afr_shift);
+	gpio->afr[afr_bank] = scratch | (altf << afr_shift);
+
+	return 0;
+}
+
+int stm32_gpio_set(u32_t *base, int pin, int value)
+{
+	struct stm32f0x_gpio *gpio = (struct stm32f0x_gpio *)base;
+
+	int pval = 1 << (pin & 0xf);
+
+	if (value) {
+		gpio->odr |= pval;
+	} else {
+		gpio->odr &= ~pval;
+	}
+
+	return 0;
+}
+
+int stm32_gpio_get(u32_t *base, int pin)
+{
+	struct stm32f0x_gpio *gpio = (struct stm32f0x_gpio *)base;
+
+	return (gpio->idr >> pin) & 0x1;
+}
+
+int stm32_gpio_enable_int(int port, int pin)
+{
+	volatile struct stm32f0x_syscfg *syscfg =
+		(struct stm32f0x_syscfg *)SYSCFG_BASE;
+	volatile union syscfg__exticr *exticr;
+
+	int shift = 0;
+
+	if (pin <= 3) {
+		exticr = &syscfg->exticr1;
+	} else if (pin <= 7) {
+		exticr = &syscfg->exticr2;
+	} else if (pin <= 11) {
+		exticr = &syscfg->exticr3;
+	} else if (pin <= 15) {
+		exticr = &syscfg->exticr4;
+	} else {
+		return -EINVAL;
+	}
+
+	shift = 4 * (pin % 4);
+
+	exticr->val &= ~(0xf << shift);
+	exticr->val |= port << shift;
+
+	return 0;
+}

soc/arm/st_stm32/stm32f0/soc_registers.h

@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2017 RnDity Sp. z o.o.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _STM32F0X_SOC_REGISTERS_H_
+#define _STM32F0X_SOC_REGISTERS_H_
+
+/* include register mapping headers */
+#include "flash_registers.h"
+#include "gpio_registers.h"
+
+#endif /* _STM32F0X_SOC_REGISTERS_H_ */

soc/arm/st_stm32/stm32f1/CMakeLists.txt

@@ -0,0 +1,5 @@
+zephyr_include_directories(${ZEPHYR_BASE}/drivers)
+zephyr_sources(
+  soc.c
+  )
+zephyr_sources_ifdef(CONFIG_GPIO soc_gpio.c)

soc/arm/st_stm32/stm32f1/Kconfig.defconfig.series

@@ -0,0 +1,29 @@
+# Kconfig - ST Microelectronics STM32F1 MCU line
+#
+# Copyright (c) 2016 Open-RnD Sp. z o.o.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_SERIES_STM32F1X
+
+source "soc/arm/st_stm32/stm32f1/Kconfig.defconfig.stm32f1*"
+
+config SOC_SERIES
+	default "stm32f1"
+
+if GPIO_STM32
+
+config GPIO_STM32_PORTD
+	default y
+
+endif # GPIO_STM32
+
+if I2C_STM32
+
+config I2C_STM32_V1
+	def_bool y
+
+endif # I2C_STM32
+
+endif # SOC_SERIES_STM32F1X

soc/arm/st_stm32/stm32f1/Kconfig.defconfig.stm32f103xx

@@ -0,0 +1,51 @@
+# Kconfig - ST Microelectronics STM32F103XX MCU
+#
+# Copyright (c) 2017, embedjournal.com
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_STM32F103XB || SOC_STM32F103X8
+
+config SOC
+	string
+	default "stm32f103xb"
+
+config NUM_IRQS
+	int
+	default 43
+
+if GPIO_STM32
+
+config GPIO_STM32_PORTE
+	default y
+
+endif # GPIO_STM32
+
+endif # SOC_STM32F103XB || SOC_STM32F103X8
+
+if SOC_STM32F103XE
+
+config SOC
+	string
+	default "stm32f103xe"
+
+config NUM_IRQS
+	int
+	default 60
+
+if GPIO_STM32
+
+config GPIO_STM32_PORTE
+	default y
+
+config GPIO_STM32_PORTF
+	default y
+
+config GPIO_STM32_PORTG
+	default y
+
+endif # GPIO_STM32
+
+endif # SOC_STM32F103XE
+

soc/arm/st_stm32/stm32f1/Kconfig.defconfig.stm32f107xc

@@ -0,0 +1,25 @@
+# Kconfig - ST Microelectronics STM32F107XC MCU
+#
+# Copyright (c) 2016 RnDity Sp. z o.o.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_STM32F107XC
+
+config SOC
+	string
+	default "stm32f107xc"
+
+config NUM_IRQS
+	int
+	default 68
+
+if GPIO_STM32
+
+config GPIO_STM32_PORTE
+	default y
+
+endif # GPIO_STM32
+
+endif # SOC_STM32F107XC

soc/arm/st_stm32/stm32f1/Kconfig.series

@@ -0,0 +1,17 @@
+# Kconfig - ST Microelectronics STM32F1 MCU series
+#
+# Copyright (c) 2016 Open-RnD Sp. z o.o.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config SOC_SERIES_STM32F1X
+	bool "STM32F1x Series MCU"
+	select CPU_CORTEX_M3
+	select SOC_FAMILY_STM32
+	select SYS_POWER_LOW_POWER_STATE_SUPPORTED
+	select HAS_STM32CUBE
+	select CPU_HAS_SYSTICK
+	select CLOCK_CONTROL_STM32_CUBE if CLOCK_CONTROL
+	help
+	 Enable support for STM32F1 MCU series

soc/arm/st_stm32/stm32f1/Kconfig.soc

@@ -0,0 +1,46 @@
+# Kconfig - ST Microelectronics STM32F1 MCU line
+#
+# Copyright (c) 2016 Open-RnD Sp. z o.o.
+# Copyright (c) RnDity Sp. z o.o.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+choice
+prompt "STM32F1x MCU Selection"
+depends on SOC_SERIES_STM32F1X
+
+config SOC_STM32F103XE
+	bool "STM32F103XE"
+	select SOC_STM32F10X_DENSITY_DEVICE
+
+config SOC_STM32F103XB
+	bool "STM32F103XB"
+	select SOC_STM32F10X_DENSITY_DEVICE
+
+config SOC_STM32F103X8
+	bool "STM32F103X8"
+	select SOC_STM32F10X_DENSITY_DEVICE
+
+config SOC_STM32F107XC
+	bool "STM32F107XC"
+	select SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE
+
+endchoice
+
+config SOC_STM32F10X_DENSITY_DEVICE
+	bool
+	help
+	 * Low density Value line devices
+	 * Medium density Value line devices
+	 * High density Value line devices
+	 * XL-density devices Value line devices
+
+config SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE
+	bool
+	help
+	 Connectivity line devices are STM32F105xx and STM32F107xx
+	 microcontrollers.  They are intended for applications where
+	 connectivity and real-time performances are required such as
+	 industrial control, control panels for security applications, UPS or
+	 home audio.  For STM32F107xx also the Ethernet MAC is available.

soc/arm/st_stm32/stm32f1/dts.fixup

@@ -0,0 +1,90 @@
+/* SoC level DTS fixup file */
+
+#define CONFIG_NUM_IRQ_PRIO_BITS                ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
+
+#define CONFIG_UART_STM32_USART_1_BASE_ADDRESS   ST_STM32_USART_40013800_BASE_ADDRESS
+#define CONFIG_UART_STM32_USART_1_BAUD_RATE      ST_STM32_USART_40013800_CURRENT_SPEED
+#define CONFIG_UART_STM32_USART_1_IRQ_PRI        ST_STM32_USART_40013800_IRQ_0_PRIORITY
+#define CONFIG_UART_STM32_USART_1_NAME           ST_STM32_USART_40013800_LABEL
+#define USART_1_IRQ                              ST_STM32_USART_40013800_IRQ_0
+
+#define CONFIG_UART_STM32_USART_2_BASE_ADDRESS   ST_STM32_USART_40004400_BASE_ADDRESS
+#define CONFIG_UART_STM32_USART_2_BAUD_RATE      ST_STM32_USART_40004400_CURRENT_SPEED
+#define CONFIG_UART_STM32_USART_2_IRQ_PRI        ST_STM32_USART_40004400_IRQ_0_PRIORITY
+#define CONFIG_UART_STM32_USART_2_NAME           ST_STM32_USART_40004400_LABEL
+#define USART_2_IRQ                              ST_STM32_USART_40004400_IRQ_0
+
+#define CONFIG_UART_STM32_USART_3_BASE_ADDRESS   ST_STM32_USART_40004800_BASE_ADDRESS
+#define CONFIG_UART_STM32_USART_3_BAUD_RATE      ST_STM32_USART_40004800_CURRENT_SPEED
+#define CONFIG_UART_STM32_USART_3_IRQ_PRI        ST_STM32_USART_40004800_IRQ_0_PRIORITY
+#define CONFIG_UART_STM32_USART_3_NAME           ST_STM32_USART_40004800_LABEL
+#define USART_3_IRQ                              ST_STM32_USART_40004800_IRQ_0
+
+#define CONFIG_UART_STM32_PORT_4_BASE_ADDRESS   ST_STM32_UART_40004C00_BASE_ADDRESS
+#define CONFIG_UART_STM32_PORT_4_BAUD_RATE      ST_STM32_UART_40004C00_CURRENT_SPEED
+#define CONFIG_UART_STM32_PORT_4_IRQ_PRI        ST_STM32_UART_40004C00_IRQ_0_PRIORITY
+#define CONFIG_UART_STM32_PORT_4_NAME           ST_STM32_UART_40004C00_LABEL
+#define PORT_4_IRQ                              ST_STM32_UART_40004C00_IRQ_0
+
+#define CONFIG_I2C_1_BASE_ADDRESS               ST_STM32_I2C_V1_40005400_BASE_ADDRESS
+#define CONFIG_I2C_1_EVENT_IRQ_PRI              ST_STM32_I2C_V1_40005400_IRQ_EVENT_PRIORITY
+#define CONFIG_I2C_1_ERROR_IRQ_PRI              ST_STM32_I2C_V1_40005400_IRQ_ERROR_PRIORITY
+#define CONFIG_I2C_1_NAME                       ST_STM32_I2C_V1_40005400_LABEL
+#define CONFIG_I2C_1_EVENT_IRQ                  ST_STM32_I2C_V1_40005400_IRQ_EVENT
+#define CONFIG_I2C_1_ERROR_IRQ                  ST_STM32_I2C_V1_40005400_IRQ_ERROR
+#define CONFIG_I2C_1_BITRATE                    ST_STM32_I2C_V1_40005400_CLOCK_FREQUENCY
+
+#define CONFIG_I2C_2_BASE_ADDRESS               ST_STM32_I2C_V1_40005800_BASE_ADDRESS
+#define CONFIG_I2C_2_EVENT_IRQ_PRI              ST_STM32_I2C_V1_40005800_IRQ_EVENT_PRIORITY
+#define CONFIG_I2C_2_ERROR_IRQ_PRI              ST_STM32_I2C_V1_40005800_IRQ_ERROR_PRIORITY
+#define CONFIG_I2C_2_NAME                       ST_STM32_I2C_V1_40005800_LABEL
+#define CONFIG_I2C_2_EVENT_IRQ                  ST_STM32_I2C_V1_40005800_IRQ_EVENT
+#define CONFIG_I2C_2_ERROR_IRQ                  ST_STM32_I2C_V1_40005800_IRQ_ERROR
+#define CONFIG_I2C_2_BITRATE                    ST_STM32_I2C_V1_40005800_CLOCK_FREQUENCY
+
+#define CONFIG_SPI_1_BASE_ADDRESS		ST_STM32_SPI_40013000_BASE_ADDRESS
+#define CONFIG_SPI_1_IRQ_PRI			ST_STM32_SPI_40013000_IRQ_0_PRIORITY
+#define CONFIG_SPI_1_NAME			ST_STM32_SPI_40013000_LABEL
+#define CONFIG_SPI_1_IRQ			ST_STM32_SPI_40013000_IRQ_0
+
+#define CONFIG_SPI_2_BASE_ADDRESS		ST_STM32_SPI_40003800_BASE_ADDRESS
+#define CONFIG_SPI_2_IRQ_PRI			ST_STM32_SPI_40003800_IRQ_0_PRIORITY
+#define CONFIG_SPI_2_NAME			ST_STM32_SPI_40003800_LABEL
+#define CONFIG_SPI_2_IRQ			ST_STM32_SPI_40003800_IRQ_0
+
+#define CONFIG_SPI_3_BASE_ADDRESS		ST_STM32_SPI_40003C00_BASE_ADDRESS
+#define CONFIG_SPI_3_IRQ_PRI			ST_STM32_SPI_40003C00_IRQ_0_PRIORITY
+#define CONFIG_SPI_3_NAME			ST_STM32_SPI_40003C00_LABEL
+#define CONFIG_SPI_3_IRQ			ST_STM32_SPI_40003C00_IRQ_0
+
+#define CONFIG_USB_BASE_ADDRESS			ST_STM32_USB_40005C00_BASE_ADDRESS
+#define CONFIG_USB_IRQ				ST_STM32_USB_40005C00_IRQ_USB
+#define CONFIG_USB_IRQ_PRI			ST_STM32_USB_40005C00_IRQ_USB_PRIORITY
+#define CONFIG_USB_NUM_BIDIR_ENDPOINTS		ST_STM32_USB_40005C00_NUM_BIDIR_ENDPOINTS
+#define CONFIG_USB_RAM_SIZE			ST_STM32_USB_40005C00_RAM_SIZE
+
+#define CONFIG_PWM_STM32_1_DEV_NAME             ST_STM32_PWM_40012C00_PWM_LABEL
+#define CONFIG_PWM_STM32_1_PRESCALER            ST_STM32_PWM_40012C00_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_2_DEV_NAME             ST_STM32_PWM_40000000_PWM_LABEL
+#define CONFIG_PWM_STM32_2_PRESCALER            ST_STM32_PWM_40000000_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_3_DEV_NAME             ST_STM32_PWM_40000400_PWM_LABEL
+#define CONFIG_PWM_STM32_3_PRESCALER            ST_STM32_PWM_40000400_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_4_DEV_NAME             ST_STM32_PWM_40000800_PWM_LABEL
+#define CONFIG_PWM_STM32_4_PRESCALER            ST_STM32_PWM_40000800_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_5_DEV_NAME             ST_STM32_PWM_40000C00_PWM_LABEL
+#define CONFIG_PWM_STM32_5_PRESCALER            ST_STM32_PWM_40000C00_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_6_DEV_NAME             ST_STM32_PWM_40001000_PWM_LABEL
+#define CONFIG_PWM_STM32_6_PRESCALER            ST_STM32_PWM_40001000_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_7_DEV_NAME             ST_STM32_PWM_40001400_PWM_LABEL
+#define CONFIG_PWM_STM32_7_PRESCALER            ST_STM32_PWM_40001400_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_8_DEV_NAME             ST_STM32_PWM_40013400_PWM_LABEL
+#define CONFIG_PWM_STM32_8_PRESCALER            ST_STM32_PWM_40013400_PWM_ST_PRESCALER
+
+/* End of SoC Level DTS fixup file */

soc/arm/st_stm32/stm32f1/flash_registers.h

@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2016 Open-RnD Sp. z o.o.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _STM32F10X_FLASH_REGISTERS_H_
+#define _STM32F10X_FLASH_REGISTERS_H_
+
+/**
+ * @brief
+ *
+ * Based on reference manual:
+ *   STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx
+ *   advanced ARM(r)-based 32-bit MCUs
+ *
+ * Chapter 3.3.3: Embedded Flash Memory
+ */
+
+enum {
+	STM32F10X_FLASH_LATENCY_0 = 0x0,
+	STM32F10X_FLASH_LATENCY_1 = 0x1,
+	STM32F10X_FLASH_LATENCY_2 = 0x2,
+};
+
+/* 3.3.3 FLASH_ACR */
+union __ef_acr {
+	u32_t val;
+	struct {
+		u32_t latency :3 __packed;
+		u32_t hlfcya :1 __packed;
+		u32_t prftbe :1 __packed;
+		u32_t prftbs :1 __packed;
+		u32_t rsvd__6_31 :26 __packed;
+	} bit;
+};
+
+/* 3.3.3 Embedded flash registers */
+struct stm32f10x_flash {
+	union __ef_acr acr;
+	u32_t keyr;
+	u32_t optkeyr;
+	u32_t sr;
+	u32_t cr;
+	u32_t ar;
+	u32_t rsvd;
+	u32_t obr;
+	u32_t wrpr;
+};
+
+#endif	/* _STM32F10X_FLASHREGISTERS_H_ */

soc/arm/st_stm32/stm32f1/gpio_registers.h

@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2016 Open-RnD Sp. z o.o.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _STM32F10X_GPIO_REGISTERS_H_
+#define _STM32F10X_GPIO_REGISTERS_H_
+
+/**
+ * @brief
+ *
+ * Based on reference manual:
+ *   STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx
+ *   advanced ARM(r)-based 32-bit MCUs
+ *
+ * Chapter 9: General-purpose and alternate-function I/Os
+ *            (GPIOs and AFIOs)
+ */
+
+/* 9.2 GPIO registers - each GPIO port controls 16 pins */
+struct stm32f10x_gpio {
+	u32_t crl;
+	u32_t crh;
+	u32_t idr;
+	u32_t odr;
+	u32_t bsrr;
+	u32_t brr;
+	u32_t lckr;
+};
+
+/* 9.4.1 AFIO_EVCR */
+union __afio_evcr {
+	u32_t val;
+	struct {
+		u32_t pin :4 __packed;
+		u32_t port :3 __packed;
+		u32_t evoe :1 __packed;
+		u32_t rsvd__8_31 :24 __packed;
+	} bit;
+};
+
+/* 9.4.2 AFIO_MAPR */
+/* TODO: support connectivity line devices */
+union __afio_mapr {
+	u32_t val;
+	struct {
+		u32_t spi1_remap :1 __packed;
+		u32_t i2c1_remap :1 __packed;
+		u32_t usart1_remap :1 __packed;
+		u32_t usart2_remap :1 __packed;
+		u32_t usart3_remap :2 __packed;
+		u32_t tim1_remap :2 __packed;
+		u32_t tim2_remap :2 __packed;
+		u32_t tim3_remap :2 __packed;
+		u32_t tim4_remap :1 __packed;
+		u32_t can_remap :2 __packed;
+		u32_t pd01_remap :1 __packed;
+		u32_t tim5ch4_iremap :1 __packed;
+		u32_t adc1_etrginj_remap :1 __packed;
+		u32_t adc1_etrgreg_remap :1 __packed;
+		u32_t adc2_etrginj_remap :1 __packed;
+		u32_t adc2_etrgreg_remap :1 __packed;
+		u32_t rsvd__21_23 :3 __packed;
+		u32_t swj_cfg :3 __packed;
+		u32_t rsvd__27_31 :5 __packed;
+	} bit;
+};
+
+/* 9.4.{3,4,5,6} AFIO_EXTICRx */
+union __afio_exticr {
+	u32_t val;
+	struct {
+		u16_t rsvd__16_31;
+		u16_t exti;
+	} bit;
+};
+
+/* 9.4.7 AFIO_MAPR2 */
+union __afio_mapr2 {
+	u32_t val;
+	struct {
+		u32_t rsvd__0_4 :5 __packed;
+		u32_t tim9_remap :1 __packed;
+		u32_t tim10_remap :1 __packed;
+		u32_t tim11_remap :1 __packed;
+		u32_t tim13_remap :1 __packed;
+		u32_t tim14_remap :1 __packed;
+		u32_t fsmc_nadv :1 __packed;
+		u32_t rsvd__11_31 :21 __packed;
+	} bit;
+};
+
+/* 9.4 AFIO registers */
+struct stm32f10x_afio {
+	union __afio_evcr evcr;
+	union __afio_mapr mapr;
+	union __afio_exticr exticr1;
+	union __afio_exticr exticr2;
+	union __afio_exticr exticr3;
+	union __afio_exticr exticr4;
+	union __afio_mapr2 mapr2;
+};
+
+#endif /* _STM32F10X_GPIO_REGISTERS_H_ */

soc/arm/st_stm32/stm32f1/linker.ld

@@ -0,0 +1,9 @@
+/* linker.ld - Linker command/script file */
+
+/*
+ * Copyright (c) 2014-2016 Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arch/arm/cortex_m/scripts/linker.ld>

soc/arm/st_stm32/stm32f1/soc.c

@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2016 Open-RnD Sp. z o.o.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for STM32F1 processor
+ */
+
+#include <device.h>
+#include <init.h>
+#include <arch/cpu.h>
+#include <cortex_m/exc.h>
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ * So the init priority has to be 0 (zero).
+ *
+ * @return 0
+ */
+static int stm32f1_init(struct device *arg)
+{
+	u32_t key;
+
+	ARG_UNUSED(arg);
+
+	key = irq_lock();
+
+	_ClearFaults();
+
+	/* Install default handler that simply resets the CPU
+	 * if configured in the kernel, NOP otherwise
+	 */
+	NMI_INIT();
+
+	irq_unlock(key);
+
+	/* Update CMSIS SystemCoreClock variable (HCLK) */
+	/* At reset, system core clock is set to 8 MHz from HSI */
+	SystemCoreClock = 8000000;
+
+	return 0;
+}
+
+SYS_INIT(stm32f1_init, PRE_KERNEL_1, 0);

soc/arm/st_stm32/stm32f1/soc.h

@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2016 Open-RnD Sp. z o.o.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file SoC configuration macros for the STM32F1 family processors.
+ *
+ * Based on reference manual:
+ *   STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx
+ *   advanced ARM(r)-based 32-bit MCUs
+ *
+ * Chapter 3.3: Memory Map
+ */
+
+
+#ifndef _STM32F1_SOC_H_
+#define _STM32F1_SOC_H_
+
+#define GPIO_REG_SIZE         0x400
+/* base address for where GPIO registers start */
+#define GPIO_PORTS_BASE       (GPIOA_BASE)
+
+#ifndef _ASMLANGUAGE
+
+#include <stm32f1xx.h>
+
+/* ARM CMSIS definitions must be included before kernel_includes.h.
+ * Therefore, it is essential to include kernel_includes.h after including
+ * core SOC-specific headers.
+ */
+#include <kernel_includes.h>
+
+#ifdef CONFIG_SERIAL_HAS_DRIVER
+#include <stm32f1xx_ll_usart.h>
+#endif
+
+#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
+#include <stm32f1xx_ll_utils.h>
+#include <stm32f1xx_ll_bus.h>
+#include <stm32f1xx_ll_rcc.h>
+#include <stm32f1xx_ll_system.h>
+#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
+
+#ifdef CONFIG_I2C
+#include <stm32f1xx_ll_i2c.h>
+#endif
+
+#ifdef CONFIG_SPI_STM32
+#include <stm32f1xx_ll_spi.h>
+#endif
+
+#ifdef CONFIG_IWDG_STM32
+#include <stm32f1xx_ll_iwdg.h>
+#endif
+
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _STM32F1_SOC_H_ */

soc/arm/st_stm32/stm32f1/soc_gpio.c

@@ -0,0 +1,184 @@
+/*
+ * Copyright (c) 2016 Open-RnD Sp. z o.o.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @brief
+ *
+ * Based on reference manual:
+ *   STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx
+ *   advanced ARM ® -based 32-bit MCUs
+ *
+ * Chapter 9: General-purpose and alternate-function I/Os
+ *            (GPIOs and AFIOs)
+ */
+
+#include <errno.h>
+
+#include <device.h>
+#include "soc.h"
+#include "soc_registers.h"
+#include <gpio.h>
+#include <gpio/gpio_stm32.h>
+#include <pinmux/stm32/pinmux_stm32.h>
+
+
+int stm32_gpio_flags_to_conf(int flags, int *pincfg)
+{
+	int direction = flags & GPIO_DIR_MASK;
+
+	if (!pincfg) {
+		return -EINVAL;
+	}
+
+	if (direction == GPIO_DIR_OUT) {
+		/* Pin is configured as an output */
+		*pincfg = (STM32_MODE_OUTPUT | STM32_CNF_GP_OUTPUT |
+			   STM32_CNF_PUSH_PULL);
+	} else {
+		/* Pin is configured as an input */
+		int pud = flags & GPIO_PUD_MASK;
+
+		/* pull-{up,down} maybe? */
+		if (pud == GPIO_PUD_PULL_UP) {
+			*pincfg = (STM32_MODE_INPUT | STM32_CNF_IN_PUPD |
+				   STM32_PUPD_PULL_UP);
+		} else if (pud == GPIO_PUD_PULL_DOWN) {
+			*pincfg = (STM32_MODE_INPUT | STM32_CNF_IN_PUPD |
+				   STM32_PUPD_PULL_DOWN);
+		} else {
+			/* floating */
+			*pincfg = (STM32_MODE_INPUT | STM32_CNF_IN_FLOAT |
+				   STM32_PUPD_NO_PULL);
+		}
+	}
+
+	return 0;
+}
+
+int stm32_gpio_configure(u32_t *base_addr, int pin, int conf, int altf)
+{
+	volatile struct stm32f10x_gpio *gpio =
+		(struct stm32f10x_gpio *)(base_addr);
+	int cnf, mode, mode_io;
+	int crpin = pin;
+
+	/* pins are configured in CRL (0-7) and CRH (8-15)
+	 * registers
+	 */
+	volatile u32_t *reg = &gpio->crl;
+
+	ARG_UNUSED(altf);
+
+	if (crpin > 7) {
+		reg = &gpio->crh;
+		crpin -= 8;
+	}
+
+	/* each port is configured by 2 registers:
+	 * CNFy[1:0]: Port x configuration bits
+	 * MODEy[1:0]: Port x mode bits
+	 *
+	 * memory layout is repeated for every port:
+	 *   |  CNF  |  MODE |
+	 *   | [0:1] | [0:1] |
+	 */
+
+	mode_io = (conf >> STM32_MODE_INOUT_SHIFT) & STM32_MODE_INOUT_MASK;
+
+	if (mode_io == STM32_MODE_INPUT) {
+		int in_pudpd = conf & (STM32_PUPD_MASK << STM32_PUPD_SHIFT);
+
+		/* Pin configured in input mode */
+		/* Mode: 00 */
+		mode = mode_io;
+		/* Configuration values: */
+		/* 00: Analog mode */
+		/* 01: Floating input */
+		/* 10: Pull-up/Pull-Down */
+		cnf = (conf >> STM32_CNF_IN_SHIFT) & STM32_CNF_IN_MASK;
+
+		if (in_pudpd == STM32_PUPD_PULL_UP) {
+			/* enable pull up */
+			gpio->odr |= 1 << pin;
+		} else if (in_pudpd == STM32_PUPD_PULL_DOWN) {
+			/* or pull down */
+			gpio->odr &= ~(1 << pin);
+		}
+	} else {
+		/* Pin configured in output mode */
+		int mode_speed = ((conf >> STM32_MODE_OSPEED_SHIFT) & \
+				  STM32_MODE_OSPEED_MASK);
+		/* Mode output possible values */
+		/* 01: Max speed 10MHz (default value) */
+		/* 10: Max speed 2MHz */
+		/* 11: Max speed 50MHz */
+		mode = mode_speed + mode_io;
+		/* Configuration possible values */
+		/* x0: Push-pull */
+		/* x1: Open-drain */
+		/* 0x: General Purpose Output */
+		/* 1x: Alternate Function Output */
+		cnf = ((conf >> STM32_CNF_OUT_0_SHIFT) & STM32_CNF_OUT_0_MASK) |
+		      (((conf >> STM32_CNF_OUT_1_SHIFT) & STM32_CNF_OUT_1_MASK)
+		       << 1);
+	}
+
+	/* clear bits */
+	*reg &= ~(0xf << (crpin * 4));
+	/* set bits */
+	*reg |= (cnf << (crpin * 4 + 2) | mode << (crpin * 4));
+
+	return 0;
+}
+
+int stm32_gpio_set(u32_t *base, int pin, int value)
+{
+	struct stm32f10x_gpio *gpio = (struct stm32f10x_gpio *)base;
+
+	int pval = 1 << (pin & 0xf);
+
+	if (value) {
+		gpio->odr |= pval;
+	} else {
+		gpio->odr &= ~pval;
+	}
+
+	return 0;
+}
+
+int stm32_gpio_get(u32_t *base, int pin)
+{
+	struct stm32f10x_gpio *gpio = (struct stm32f10x_gpio *)base;
+
+	return (gpio->idr >> pin) & 0x1;
+}
+
+int stm32_gpio_enable_int(int port, int pin)
+{
+	volatile struct stm32f10x_afio *afio =
+		(struct stm32f10x_afio *)AFIO_BASE;
+	volatile union __afio_exticr *exticr;
+	int shift = 0;
+
+	if (pin <= 3) {
+		exticr = &afio->exticr1;
+	} else if (pin <= 7) {
+		exticr = &afio->exticr2;
+	} else if (pin <= 11) {
+		exticr = &afio->exticr3;
+	} else if (pin <= 15) {
+		exticr = &afio->exticr4;
+	} else {
+		return -EINVAL;
+	}
+
+	shift = 4 * (pin % 4);
+
+	exticr->val &= ~(0xf << shift);
+	exticr->val |= port << shift;
+
+	return 0;
+}

soc/arm/st_stm32/stm32f1/soc_registers.h

@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2016 Open-RnD Sp. z o.o.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _STM32F10X_SOC_REGISTERS_H_
+#define _STM32F10X_SOC_REGISTERS_H_
+
+/* include register mapping headers */
+#include "gpio_registers.h"
+#include "flash_registers.h"
+
+#endif /* _STM32F10X_SOC_REGISTERS_H_ */

soc/arm/st_stm32/stm32f2/CMakeLists.txt

@@ -0,0 +1,5 @@
+zephyr_include_directories(${ZEPHYR_BASE}/drivers)
+zephyr_sources(
+  soc.c
+  )
+zephyr_sources_ifdef(CONFIG_GPIO soc_gpio.c)

soc/arm/st_stm32/stm32f2/Kconfig.defconfig.series

@@ -0,0 +1,37 @@
+# Kconfig - ST Microelectronics STM32F2 MCU line
+#
+# Copyright (c) 2018 qianfan Zhao <qianfanguijin@163.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_SERIES_STM32F2X
+
+source "soc/arm/st_stm32/stm32f2/Kconfig.defconfig.stm32f2*"
+
+config SOC_SERIES
+	default "stm32f2"
+
+if GPIO_STM32
+
+config GPIO_STM32_PORTD
+	default y
+
+config GPIO_STM32_PORTE
+	default y
+
+config GPIO_STM32_PORTF
+	default y
+
+config GPIO_STM32_PORTG
+	default y
+
+config GPIO_STM32_PORTH
+	default y
+
+config GPIO_STM32_PORTI
+	default y
+
+endif # GPIO_STM32
+
+endif # SOC_SERIES_STM32F2X

soc/arm/st_stm32/stm32f2/Kconfig.defconfig.stm32f207xx

@@ -0,0 +1,18 @@
+# Kconfig - ST Microelectronics stm32f207 MCU
+#
+# Copyright (c) 2018 qianfan Zhao <qianfanguijin@163.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_STM32F207XE || SOC_STM32F207XG
+
+config SOC
+	string
+	default "STM32F207xx"
+
+config NUM_IRQS
+	int
+	default 81
+
+endif

soc/arm/st_stm32/stm32f2/Kconfig.series

@@ -0,0 +1,18 @@
+# Kconfig - ST Microelectronics STM32F2X MCU series
+#
+# Copyright (c) 2018 qianfan Zhao <qianfanguijin@163.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config SOC_SERIES_STM32F2X
+	bool "stm32f2x Series MCU"
+	select CPU_CORTEX_M
+	select CPU_CORTEX_M3
+	select SOC_FAMILY_STM32
+	select SYS_POWER_LOW_POWER_STATE_SUPPORTED
+	select HAS_STM32CUBE
+	select CPU_HAS_SYSTICK
+	select CLOCK_CONTROL_STM32_CUBE if CLOCK_CONTROL
+	help
+	  Enable support for stm32f2 MCU series

soc/arm/st_stm32/stm32f2/Kconfig.soc

@@ -0,0 +1,18 @@
+# Kconfig - ST Microelectronics stm32f2 MCU line
+#
+# Copyright (c) 2018 qianfan Zhao <qianfanguijin@163.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+choice
+prompt "STM32F2X MCU Selection"
+depends on SOC_SERIES_STM32F2X
+
+config SOC_STM32F207XE
+	bool "STM32F207XE"
+
+config SOC_STM32F207XG
+	bool "STM32F207XG"
+
+endchoice

soc/arm/st_stm32/stm32f2/dts.fixup

@@ -0,0 +1,47 @@
+/* SoC level DTS fixup file */
+
+#define CONFIG_NUM_IRQ_PRIO_BITS		ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
+
+#define CONFIG_UART_STM32_USART_1_BASE_ADDRESS	ST_STM32_USART_40011000_BASE_ADDRESS
+#define CONFIG_UART_STM32_USART_1_BAUD_RATE	ST_STM32_USART_40011000_CURRENT_SPEED
+#define CONFIG_UART_STM32_USART_1_IRQ_PRI	ST_STM32_USART_40011000_IRQ_0_PRIORITY
+#define CONFIG_UART_STM32_USART_1_NAME		ST_STM32_USART_40011000_LABEL
+#define USART_1_IRQ				ST_STM32_USART_40011000_IRQ_0
+
+#define CONFIG_UART_STM32_USART_2_BASE_ADDRESS	ST_STM32_USART_40004400_BASE_ADDRESS
+#define CONFIG_UART_STM32_USART_2_BAUD_RATE	ST_STM32_USART_40004400_CURRENT_SPEED
+#define CONFIG_UART_STM32_USART_2_IRQ_PRI	ST_STM32_USART_40004400_IRQ_0_PRIORITY
+#define CONFIG_UART_STM32_USART_2_NAME		ST_STM32_USART_40004400_LABEL
+#define USART_2_IRQ				ST_STM32_USART_40004400_IRQ_0
+
+#define CONFIG_UART_STM32_USART_3_BASE_ADDRESS   ST_STM32_USART_40004800_BASE_ADDRESS
+#define CONFIG_UART_STM32_USART_3_BAUD_RATE      ST_STM32_USART_40004800_CURRENT_SPEED
+#define CONFIG_UART_STM32_USART_3_IRQ_PRI        ST_STM32_USART_40004800_IRQ_0_PRIORITY
+#define CONFIG_UART_STM32_USART_3_NAME           ST_STM32_USART_40004800_LABEL
+#define USART_3_IRQ                              ST_STM32_USART_40004800_IRQ_0
+
+#define CONFIG_UART_STM32_USART_6_NAME           ST_STM32_USART_40011400_LABEL
+#define CONFIG_UART_STM32_USART_6_BASE_ADDRESS   ST_STM32_USART_40011400_BASE_ADDRESS
+#define CONFIG_UART_STM32_USART_6_BAUD_RATE      ST_STM32_USART_40011400_CURRENT_SPEED
+#define CONFIG_UART_STM32_USART_6_IRQ_PRI        ST_STM32_USART_40011400_IRQ_0_PRIORITY
+#define USART_6_IRQ                              ST_STM32_USART_40011400_IRQ_0
+
+#define CONFIG_UART_STM32_UART_4_NAME		ST_STM32_UART_40004C00_LABEL
+#define CONFIG_UART_STM32_UART_4_BASE_ADDRESS	ST_STM32_UART_40004C00_BASE_ADDRESS
+#define CONFIG_UART_STM32_UART_4_BAUD_RATE	ST_STM32_UART_40004C00_CURRENT_SPEED
+#define CONFIG_UART_STM32_UART_4_IRQ_PRI	ST_STM32_UART_40004C00_IRQ_0_PRIORITY
+#define UART_4_IRQ				ST_STM32_UART_40004C00_IRQ_0
+
+#define CONFIG_UART_STM32_UART_5_NAME		ST_STM32_UART_40005000_LABEL
+#define CONFIG_UART_STM32_UART_5_BASE_ADDRESS	ST_STM32_UART_40005000_BASE_ADDRESS
+#define CONFIG_UART_STM32_UART_5_BAUD_RATE	ST_STM32_UART_40005000_CURRENT_SPEED
+#define CONFIG_UART_STM32_UART_5_IRQ_PRI	ST_STM32_UART_40005000_IRQ_0_PRIORITY
+#define UART_5_IRQ				ST_STM32_UART_40005000_IRQ_0
+
+#define CONFIG_USB_BASE_ADDRESS			ST_STM32_OTGFS_50000000_BASE_ADDRESS
+#define CONFIG_USB_IRQ				ST_STM32_OTGFS_50000000_IRQ_OTGFS
+#define CONFIG_USB_IRQ_PRI			ST_STM32_OTGFS_50000000_IRQ_OTGFS_PRIORITY
+#define CONFIG_USB_NUM_BIDIR_ENDPOINTS		ST_STM32_OTGFS_50000000_NUM_BIDIR_ENDPOINTS
+#define CONFIG_USB_RAM_SIZE			ST_STM32_OTGFS_50000000_RAM_SIZE
+
+/* End of SoC Level DTS fixup file */

soc/arm/st_stm32/stm32f2/gpio_registers.h

@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2018 qianfan Zhao <qianfanguijin@163.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _STM32F2X_GPIO_REGISTERS_H_
+#define _STM32F2X_GPIO_REGISTERS_H_
+
+/**
+ * @brief
+ *
+ * Based on reference manual:
+ *   stm32f2X advanced ARM ® -based 32-bit MCUs
+
+ *
+ * Chapter 6: General-purpose I/Os (GPIO)
+ * Chapter 7: System configuration controller (SYSCFG)
+ */
+
+struct stm32f2x_gpio {
+	u32_t moder;
+	u32_t otyper;
+	u32_t ospeedr;
+	u32_t pupdr;
+	u32_t idr;
+	u32_t odr;
+	u32_t bsrr;
+	u32_t lckr;
+	u32_t afr[2];
+};
+
+union syscfg_exticr {
+	u32_t val;
+	struct {
+		u16_t rsvd__16_31;
+		u16_t exti;
+	} bit;
+};
+
+/* 7.2 SYSCFG registers */
+struct stm32f2x_syscfg {
+	u32_t memrmp;
+	u32_t pmc;
+	union syscfg_exticr exticr1;
+	union syscfg_exticr exticr2;
+	union syscfg_exticr exticr3;
+	union syscfg_exticr exticr4;
+	u32_t cmpcr;
+};
+
+#endif /* _STM32F2X_GPIO_REGISTERS_H_ */

soc/arm/st_stm32/stm32f2/linker.ld

@@ -0,0 +1,9 @@
+/* linker.ld - Linker command/script file */
+
+/*
+ * Copyright (c) 2018 qianfan Zhao <qianfanguijin@163.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arch/arm/cortex_m/scripts/linker.ld>

soc/arm/st_stm32/stm32f2/soc.c

@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2018 qianfan Zhao <qianfanguijin@163.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for stm32f2 processor
+ */
+
+#include <kernel.h>
+#include <device.h>
+#include <init.h>
+#include <soc.h>
+#include <arch/cpu.h>
+#include <cortex_m/exc.h>
+#include <linker/linker-defs.h>
+#include <string.h>
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ * So the init priority has to be 0 (zero).
+ *
+ * @return 0
+ */
+static int stm32f2_init(struct device *arg)
+{
+	u32_t key;
+
+	ARG_UNUSED(arg);
+
+	key = irq_lock();
+
+	_ClearFaults();
+
+	/* Install default handler that simply resets the CPU
+	 * if configured in the kernel, NOP otherwise
+	 */
+	NMI_INIT();
+
+	irq_unlock(key);
+
+	/* Update CMSIS SystemCoreClock variable (HCLK) */
+	/* At reset, system core clock is set to 16 MHz from HSI */
+	SystemCoreClock = 16000000;
+
+	return 0;
+}
+
+SYS_INIT(stm32f2_init, PRE_KERNEL_1, 0);

soc/arm/st_stm32/stm32f2/soc.h

@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2018 qianfan Zhao <qianfanguijin@163.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file SoC configuration macros for the stm32f2 family processors.
+ *
+ * Based on reference manual:
+ *   stm32f2X advanced ARM ® -based 32-bit MCUs
+ *
+ * Chapter 2.2: Memory organization
+ */
+
+
+#ifndef _STM32F2_SOC_H_
+#define _STM32F2_SOC_H_
+
+#define GPIO_REG_SIZE         0x400
+/* base address for where GPIO registers start */
+#define GPIO_PORTS_BASE       (GPIOA_BASE)
+
+#ifndef _ASMLANGUAGE
+
+#include <stm32f2xx.h>
+
+/* ARM CMSIS definitions must be included before kernel_includes.h.
+ * Therefore, it is essential to include kernel_includes.h after including
+ * core SOC-specific headers.
+ */
+#include <kernel_includes.h>
+
+#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
+#include <stm32f2xx_ll_utils.h>
+#include <stm32f2xx_ll_bus.h>
+#include <stm32f2xx_ll_rcc.h>
+#include <stm32f2xx_ll_system.h>
+#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
+
+#ifdef CONFIG_SERIAL_HAS_DRIVER
+#include <stm32f2xx_ll_usart.h>
+#endif
+
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _STM32F2_SOC_H_ */

soc/arm/st_stm32/stm32f2/soc_gpio.c

@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2018 qianfan Zhao <qianfanguijin@163.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @brief
+ *
+ * Based on reference manual:
+ *   STM32F205xx, STM32F207xx, STM32F215xx and STM32F217xx
+ *   advanced ARM-based 32-bit MCUs
+ *
+ * Chapter 6: General-purpose I/Os (GPIO)
+ */
+
+#include <errno.h>
+
+#include <device.h>
+#include "soc.h"
+#include "soc_registers.h"
+#include <gpio.h>
+#include <gpio/gpio_stm32.h>
+
+int stm32_gpio_flags_to_conf(int flags, int *pincfg)
+{
+	int direction = flags & GPIO_DIR_MASK;
+	int pud = flags & GPIO_PUD_MASK;
+
+	if (!pincfg) {
+		return -EINVAL;
+	}
+
+	if (direction == GPIO_DIR_OUT) {
+		*pincfg = STM32_MODER_OUTPUT_MODE;
+	} else {
+		/* pull-{up,down} maybe? */
+		*pincfg = STM32_MODER_INPUT_MODE;
+		if (pud == GPIO_PUD_PULL_UP) {
+			*pincfg = *pincfg | STM32_PUPDR_PULL_UP;
+		} else if (pud == GPIO_PUD_PULL_DOWN) {
+			*pincfg = *pincfg | STM32_PUPDR_PULL_DOWN;
+		} else {
+			/* floating */
+			*pincfg = *pincfg | STM32_PUPDR_NO_PULL;
+		}
+	}
+
+	return 0;
+}
+
+int stm32_gpio_configure(u32_t *base_addr, int pin, int conf, int altf)
+{
+	volatile struct stm32f2x_gpio *gpio =
+		(struct stm32f2x_gpio *)(base_addr);
+	unsigned int mode, otype, ospeed, pupd;
+	unsigned int pin_shift = pin << 1;
+	unsigned int afr_bank = pin / 8;
+	unsigned int afr_shift = (pin % 8) << 2;
+	u32_t scratch;
+
+	mode = (conf >> STM32_MODER_SHIFT) & STM32_MODER_MASK;
+	otype = (conf >> STM32_OTYPER_SHIFT) & STM32_OTYPER_MASK;
+	ospeed = (conf >> STM32_OSPEEDR_SHIFT) & STM32_OSPEEDR_MASK;
+	pupd = (conf >> STM32_PUPDR_SHIFT) & STM32_PUPDR_MASK;
+
+	scratch = gpio->moder & ~(STM32_MODER_MASK << pin_shift);
+	gpio->moder = scratch | (mode << pin_shift);
+
+	scratch = gpio->ospeedr & ~(STM32_OSPEEDR_MASK << pin_shift);
+	gpio->ospeedr = scratch | (ospeed << pin_shift);
+
+	scratch = gpio->otyper & ~(STM32_OTYPER_MASK << pin);
+	gpio->otyper = scratch | (otype << pin);
+
+	scratch = gpio->pupdr & ~(STM32_PUPDR_MASK << pin_shift);
+	gpio->pupdr = scratch | (pupd << pin_shift);
+
+	scratch = gpio->afr[afr_bank] & ~(STM32_AFR_MASK << afr_shift);
+	gpio->afr[afr_bank] = scratch | (altf << afr_shift);
+
+	return 0;
+}
+
+int stm32_gpio_set(u32_t *base, int pin, int value)
+{
+	struct stm32f2x_gpio *gpio = (struct stm32f2x_gpio *)base;
+
+	int pval = 1 << (pin & 0xf);
+
+	if (value) {
+		gpio->odr |= pval;
+	} else {
+		gpio->odr &= ~pval;
+	}
+
+	return 0;
+}
+
+int stm32_gpio_get(u32_t *base, int pin)
+{
+	struct stm32f2x_gpio *gpio = (struct stm32f2x_gpio *)base;
+
+	return (gpio->idr >> pin) & 0x1;
+}
+
+int stm32_gpio_enable_int(int port, int pin)
+{
+	volatile struct stm32f2x_syscfg *syscfg =
+		(struct stm32f2x_syscfg *)SYSCFG_BASE;
+	volatile union syscfg_exticr *exticr;
+
+	/* Enable System Configuration Controller clock. */
+	struct device *clk =
+		device_get_binding(STM32_CLOCK_CONTROL_NAME);
+
+	struct stm32_pclken pclken = {
+		.bus = STM32_CLOCK_BUS_APB2,
+		.enr = LL_APB2_GRP1_PERIPH_SYSCFG
+	};
+
+	clock_control_on(clk, (clock_control_subsys_t *) &pclken);
+
+	int shift = 0;
+
+	if (pin <= 3) {
+		exticr = &syscfg->exticr1;
+	} else if (pin <= 7) {
+		exticr = &syscfg->exticr2;
+	} else if (pin <= 11) {
+		exticr = &syscfg->exticr3;
+	} else if (pin <= 15) {
+		exticr = &syscfg->exticr4;
+	} else {
+		return -EINVAL;
+	}
+
+	shift = 4 * (pin % 4);
+
+	exticr->val &= ~(0xf << shift);
+	exticr->val |= port << shift;
+
+	return 0;
+}

soc/arm/st_stm32/stm32f2/soc_registers.h

@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2018 qianfan Zhao <qianfanguijin@163.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _STM32F2X_SOC_REGISTERS_H_
+#define _STM32F2X_SOC_REGISTERS_H_
+
+/* include register mapping headers */
+#include "gpio_registers.h"
+
+#endif /* _STM32F2X_SOC_REGISTERS_H_ */

soc/arm/st_stm32/stm32f3/CMakeLists.txt

@@ -0,0 +1,5 @@
+zephyr_include_directories(${ZEPHYR_BASE}/drivers)
+zephyr_sources(
+  soc.c
+  )
+zephyr_sources_ifdef(CONFIG_GPIO soc_gpio.c)

soc/arm/st_stm32/stm32f3/Kconfig.defconfig.series

@@ -0,0 +1,29 @@
+# Kconfig - ST Microelectronics STM32F3 MCU line
+#
+# Copyright (c) 2016 RnDity Sp. z o.o.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_SERIES_STM32F3X
+
+source "soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f3*"
+
+config SOC_SERIES
+	default "stm32f3"
+
+if GPIO_STM32
+
+config GPIO_STM32_PORTD
+	default y
+
+endif # GPIO_STM32
+
+if I2C_STM32
+
+config I2C_STM32_V2
+	def_bool y
+
+endif # I2C_STM32
+
+endif # SOC_SERIES_STM32F3X

soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f303xc

@@ -0,0 +1,32 @@
+# Kconfig - ST Microelectronics STM32F303XC MCU
+#
+# Copyright (c) 2016 RnDity Sp. z o.o.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_STM32F303XC
+
+config SOC
+	string
+	default "stm32f303xc"
+
+config FLASH_PAGE_SIZE
+	hex
+	default 0x800
+
+config NUM_IRQS
+	int
+	default 82
+
+if GPIO_STM32
+
+config GPIO_STM32_PORTE
+	default y
+
+config GPIO_STM32_PORTF
+	default y
+
+endif # GPIO_STM32
+
+endif # SOC_STM32F303XC

soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f334x8

@@ -0,0 +1,29 @@
+# Kconfig - ST Microelectronics STM32F334X8 MCU
+#
+# Copyright (c) 2016 RnDity Sp. z o.o.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_STM32F334X8
+
+config SOC
+	string
+	default "stm32f334x8"
+
+config FLASH_PAGE_SIZE
+	hex
+	default 0x800
+
+config NUM_IRQS
+	int
+	default 82
+
+if GPIO_STM32
+
+config GPIO_STM32_PORTF
+	default y
+
+endif # GPIO_STM32
+
+endif # SOC_STM32F334X8

soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f373xc

@@ -0,0 +1,32 @@
+# Kconfig - ST Microelectronics STM32F373XC MCU
+#
+# Copyright (c) 2016 RnDity Sp. z o.o.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_STM32F373XC
+
+config SOC
+	string
+	default "stm32f373xc"
+
+config FLASH_PAGE_SIZE
+	hex
+	default 0x800
+
+config NUM_IRQS
+	int
+	default 82
+
+if GPIO_STM32
+
+config GPIO_STM32_PORTE
+	default y
+
+config GPIO_STM32_PORTF
+	default y
+
+endif # GPIO_STM32
+
+endif # SOC_STM32F373XC

soc/arm/st_stm32/stm32f3/Kconfig.series

@@ -0,0 +1,18 @@
+# Kconfig - ST Microelectronics STM32F3 MCU series
+#
+# Copyright (c) 2016 RnDity Sp. z o.o.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config SOC_SERIES_STM32F3X
+	bool "STM32F3x Series MCU"
+	select CPU_CORTEX_M4
+	select SOC_FAMILY_STM32
+	select SYS_POWER_LOW_POWER_STATE_SUPPORTED
+	select CPU_HAS_FPU
+	select CPU_HAS_SYSTICK
+	select HAS_STM32CUBE
+	select CLOCK_CONTROL_STM32_CUBE if CLOCK_CONTROL
+	help
+	 Enable support for STM32F3 MCU series

soc/arm/st_stm32/stm32f3/Kconfig.soc

@@ -0,0 +1,23 @@
+# Kconfig - ST Microelectronics STM32F3 MCU line
+#
+# Copyright (c) 2016 RnDity Sp. z o.o.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+choice
+prompt "STM32F3x MCU Selection"
+depends on SOC_SERIES_STM32F3X
+
+config SOC_STM32F303XC
+	bool "STM32F303XC"
+	select CPU_HAS_MPU
+
+config SOC_STM32F334X8
+	bool "STM32F334X8"
+
+config SOC_STM32F373XC
+	bool "STM32F373XC"
+	select CPU_HAS_MPU
+
+endchoice

soc/arm/st_stm32/stm32f3/dts.fixup

@@ -0,0 +1,113 @@
+/* SoC level DTS fixup file */
+
+#define CONFIG_NUM_IRQ_PRIO_BITS                ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
+
+#define CONFIG_UART_STM32_USART_1_BASE_ADDRESS   ST_STM32_USART_40013800_BASE_ADDRESS
+#define CONFIG_UART_STM32_USART_1_BAUD_RATE      ST_STM32_USART_40013800_CURRENT_SPEED
+#define CONFIG_UART_STM32_USART_1_IRQ_PRI        ST_STM32_USART_40013800_IRQ_0_PRIORITY
+#define CONFIG_UART_STM32_USART_1_NAME           ST_STM32_USART_40013800_LABEL
+#define USART_1_IRQ                              ST_STM32_USART_40013800_IRQ_0
+
+#define CONFIG_UART_STM32_USART_2_BASE_ADDRESS   ST_STM32_USART_40004400_BASE_ADDRESS
+#define CONFIG_UART_STM32_USART_2_BAUD_RATE      ST_STM32_USART_40004400_CURRENT_SPEED
+#define CONFIG_UART_STM32_USART_2_IRQ_PRI        ST_STM32_USART_40004400_IRQ_0_PRIORITY
+#define CONFIG_UART_STM32_USART_2_NAME           ST_STM32_USART_40004400_LABEL
+#define USART_2_IRQ                              ST_STM32_USART_40004400_IRQ_0
+
+#define CONFIG_I2C_1_BASE_ADDRESS               ST_STM32_I2C_V2_40005400_BASE_ADDRESS
+#define CONFIG_I2C_1_EVENT_IRQ_PRI              ST_STM32_I2C_V2_40005400_IRQ_EVENT_PRIORITY
+#define CONFIG_I2C_1_ERROR_IRQ_PRI              ST_STM32_I2C_V2_40005400_IRQ_ERROR_PRIORITY
+#define CONFIG_I2C_1_NAME                       ST_STM32_I2C_V2_40005400_LABEL
+#define CONFIG_I2C_1_EVENT_IRQ                  ST_STM32_I2C_V2_40005400_IRQ_EVENT
+#define CONFIG_I2C_1_ERROR_IRQ                  ST_STM32_I2C_V2_40005400_IRQ_ERROR
+#define CONFIG_I2C_1_BITRATE                    ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY
+
+#define CONFIG_I2C_2_BASE_ADDRESS               ST_STM32_I2C_V2_40005800_BASE_ADDRESS
+#define CONFIG_I2C_2_EVENT_IRQ_PRI              ST_STM32_I2C_V2_40005800_IRQ_EVENT_PRIORITY
+#define CONFIG_I2C_2_ERROR_IRQ_PRI              ST_STM32_I2C_V2_40005800_IRQ_ERROR_PRIORITY
+#define CONFIG_I2C_2_NAME                       ST_STM32_I2C_V2_40005800_LABEL
+#define CONFIG_I2C_2_EVENT_IRQ                  ST_STM32_I2C_V2_40005800_IRQ_EVENT
+#define CONFIG_I2C_2_ERROR_IRQ                  ST_STM32_I2C_V2_40005800_IRQ_ERROR
+#define CONFIG_I2C_2_BITRATE                    ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY
+
+#define CONFIG_SPI_1_BASE_ADDRESS		ST_STM32_SPI_FIFO_40013000_BASE_ADDRESS
+#define CONFIG_SPI_1_IRQ_PRI			ST_STM32_SPI_FIFO_40013000_IRQ_0_PRIORITY
+#define CONFIG_SPI_1_NAME			ST_STM32_SPI_FIFO_40013000_LABEL
+#define CONFIG_SPI_1_IRQ			ST_STM32_SPI_FIFO_40013000_IRQ_0
+
+#define CONFIG_SPI_2_BASE_ADDRESS		ST_STM32_SPI_FIFO_40003800_BASE_ADDRESS
+#define CONFIG_SPI_2_IRQ_PRI			ST_STM32_SPI_FIFO_40003800_IRQ_0_PRIORITY
+#define CONFIG_SPI_2_NAME			ST_STM32_SPI_FIFO_40003800_LABEL
+#define CONFIG_SPI_2_IRQ			ST_STM32_SPI_FIFO_40003800_IRQ_0
+
+#define CONFIG_SPI_3_BASE_ADDRESS		ST_STM32_SPI_FIFO_40003C00_BASE_ADDRESS
+#define CONFIG_SPI_3_IRQ_PRI			ST_STM32_SPI_FIFO_40003C00_IRQ_0_PRIORITY
+#define CONFIG_SPI_3_NAME			ST_STM32_SPI_FIFO_40003C00_LABEL
+#define CONFIG_SPI_3_IRQ			ST_STM32_SPI_FIFO_40003C00_IRQ_0
+
+#define CONFIG_SPI_4_BASE_ADDRESS		ST_STM32_SPI_FIFO_40013C00_BASE_ADDRESS
+#define CONFIG_SPI_4_IRQ_PRI			ST_STM32_SPI_FIFO_40013C00_IRQ_0_PRIORITY
+#define CONFIG_SPI_4_NAME			ST_STM32_SPI_FIFO_40013C00_LABEL
+#define CONFIG_SPI_4_IRQ			ST_STM32_SPI_FIFO_40013C00_IRQ_0
+
+#define FLASH_DEV_BASE_ADDRESS		        ST_STM32F3_FLASH_CONTROLLER_40022000_BASE_ADDRESS
+#define FLASH_DEV_NAME			        ST_STM32F3_FLASH_CONTROLLER_40022000_LABEL
+
+#define CONFIG_USB_BASE_ADDRESS			ST_STM32_USB_40005C00_BASE_ADDRESS
+#define CONFIG_USB_IRQ				ST_STM32_USB_40005C00_IRQ_USB
+#define CONFIG_USB_IRQ_PRI			ST_STM32_USB_40005C00_IRQ_USB_PRIORITY
+#define CONFIG_USB_NUM_BIDIR_ENDPOINTS		ST_STM32_USB_40005C00_NUM_BIDIR_ENDPOINTS
+#define CONFIG_USB_RAM_SIZE			ST_STM32_USB_40005C00_RAM_SIZE
+
+#define CONFIG_PWM_STM32_1_DEV_NAME             ST_STM32_PWM_40012C00_PWM_LABEL
+#define CONFIG_PWM_STM32_1_PRESCALER            ST_STM32_PWM_40012C00_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_2_DEV_NAME             ST_STM32_PWM_40000000_PWM_LABEL
+#define CONFIG_PWM_STM32_2_PRESCALER            ST_STM32_PWM_40000000_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_3_DEV_NAME             ST_STM32_PWM_40000400_PWM_LABEL
+#define CONFIG_PWM_STM32_3_PRESCALER            ST_STM32_PWM_40000400_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_4_DEV_NAME             ST_STM32_PWM_40000800_PWM_LABEL
+#define CONFIG_PWM_STM32_4_PRESCALER            ST_STM32_PWM_40000800_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_5_DEV_NAME             ST_STM32_PWM_40000C00_PWM_LABEL
+#define CONFIG_PWM_STM32_5_PRESCALER            ST_STM32_PWM_40000C00_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_6_DEV_NAME             ST_STM32_PWM_40001000_PWM_LABEL
+#define CONFIG_PWM_STM32_6_PRESCALER            ST_STM32_PWM_40001000_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_7_DEV_NAME             ST_STM32_PWM_40001400_PWM_LABEL
+#define CONFIG_PWM_STM32_7_PRESCALER            ST_STM32_PWM_40001400_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_8_DEV_NAME             ST_STM32_PWM_40013400_PWM_LABEL
+#define CONFIG_PWM_STM32_8_PRESCALER            ST_STM32_PWM_40013400_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_12_DEV_NAME            ST_STM32_PWM_40001800_PWM_LABEL
+#define CONFIG_PWM_STM32_12_PRESCALER           ST_STM32_PWM_40001800_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_13_DEV_NAME            ST_STM32_PWM_40001C00_PWM_LABEL
+#define CONFIG_PWM_STM32_13_PRESCALER           ST_STM32_PWM_40001C00_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_14_DEV_NAME            ST_STM32_PWM_40002000_PWM_LABEL
+#define CONFIG_PWM_STM32_14_PRESCALER           ST_STM32_PWM_40002000_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_15_DEV_NAME            ST_STM32_PWM_40014000_PWM_LABEL
+#define CONFIG_PWM_STM32_15_PRESCALER           ST_STM32_PWM_40014000_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_16_DEV_NAME            ST_STM32_PWM_40014400_PWM_LABEL
+#define CONFIG_PWM_STM32_16_PRESCALER           ST_STM32_PWM_40014400_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_17_DEV_NAME            ST_STM32_PWM_40014800_PWM_LABEL
+#define CONFIG_PWM_STM32_17_PRESCALER           ST_STM32_PWM_40014800_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_18_DEV_NAME            ST_STM32_PWM_40009C00_PWM_LABEL
+#define CONFIG_PWM_STM32_18_PRESCALER           ST_STM32_PWM_40009C00_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_19_DEV_NAME            ST_STM32_PWM_40015C00_PWM_LABEL
+#define CONFIG_PWM_STM32_19_PRESCALER           ST_STM32_PWM_40015C00_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_20_DEV_NAME            ST_STM32_PWM_40015000_PWM_LABEL
+#define CONFIG_PWM_STM32_20_PRESCALER           ST_STM32_PWM_40015000_PWM_ST_PRESCALER
+
+/* End of SoC Level DTS fixup file */

soc/arm/st_stm32/stm32f3/flash_registers.h

@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2016 RnDity Sp. z o.o.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _STM32F3X_FLASH_REGISTERS_H_
+#define _STM32F3X_FLASH_REGISTERS_H_
+
+#include <zephyr/types.h>
+
+/**
+ * @brief
+ *
+ * Based on reference manual:
+ *   STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx
+ *   advanced ARM(r)-based 32-bit MCUs
+ *   &
+ *   STM32F334xx advanced ARM(r)-based 32-bit MCUs
+ *
+ * Chapter 3.3.3: Embedded Flash Memory
+ */
+
+enum {
+	STM32_FLASH_LATENCY_0 = 0x0,
+	STM32_FLASH_LATENCY_1 = 0x1,
+	STM32_FLASH_LATENCY_2 = 0x2,
+};
+
+/* 3.3.3 FLASH_ACR */
+union ef_acr {
+	u32_t val;
+	struct {
+		u32_t latency :3 __packed;
+		u32_t hlfcya :1 __packed;
+		u32_t prftbe :1 __packed;
+		u32_t prftbs :1 __packed;
+		u32_t rsvd__6_31 :26 __packed;
+	} bit;
+};
+
+/* 3.3.3 Embedded flash registers */
+struct stm32_flash {
+	union ef_acr acr;
+	u32_t keyr;
+	u32_t optkeyr;
+	u32_t sr;
+	u32_t cr;
+	u32_t ar;
+	u32_t rsvd;
+	u32_t obr;
+	u32_t wrpr;
+};
+
+/* list of device commands */
+enum stm32_embedded_flash_cmd {
+	STM32_FLASH_CMD_LATENCY_FOR_CLOCK_SET,
+};
+
+#endif /* _STM32F3X_FLASH_REGISTERS_H_ */

soc/arm/st_stm32/stm32f3/gpio_registers.h

@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2016 RnDity Sp. z o.o.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _STM32F3X_GPIO_REGISTERS_H_
+#define _STM32F3X_GPIO_REGISTERS_H_
+
+/**
+ * @brief
+ *
+ * Based on reference manual:
+ *   STM32F303xB/C/D/E, STM32F303x6/8, STM32F328x8, STM32F358xC,
+ *   STM32F398xE advanced ARM(r)-based MCUs
+ *
+ * Chapter 11: General-purpose I/Os
+ */
+
+struct stm32f3x_gpio {
+	u32_t moder;
+	u32_t otyper;
+	u32_t ospeedr;
+	u32_t pupdr;
+	u32_t idr;
+	u32_t odr;
+	u32_t bsrr;
+	u32_t lckr;
+	u32_t afr[2];
+	u32_t brr;
+};
+
+union syscfg_cfgr1 {
+	u32_t val;
+	struct {
+		u32_t mem_mode :2 __packed;
+		u32_t rsvd__2_5 :4 __packed;
+		u32_t tim1_itr3_rmo :1 __packed;
+		u32_t dac_trig_rmp :1 __packed;
+		u32_t rsvd__8_10 :3 __packed;
+		u32_t tim16_dma_rmp :1 __packed;
+		u32_t tim17_dma_rmp :1 __packed;
+		u32_t tim16_dac1_dma_rmp :1 __packed;
+		u32_t tim17_dac2_dma_rmp :1 __packed;
+		u32_t dac2_ch1_dma_rmp :1 __packed;
+		u32_t i2c_pb6_fmp :1 __packed;
+		u32_t i2c_pb7_fmp :1 __packed;
+		u32_t i2c_pb8_fmp :1 __packed;
+		u32_t i2c_pb9_fmp :1 __packed;
+		u32_t i2c1_fmp :1 __packed;
+		u32_t rsvd__21 :1 __packed;
+		u32_t encoder_mode :2 __packed;
+		u32_t rsvd__24_25 :2 __packed;
+		u32_t fpu_ie :6 __packed;
+	} bit;
+};
+
+union syscfg_rcr {
+	u32_t val;
+	struct {
+		u32_t page0_wp :1 __packed;
+		u32_t page1_wp :1 __packed;
+		u32_t page2_wp :1 __packed;
+		u32_t page3_wp :1 __packed;
+		u32_t rsvd__4_31 :28 __packed;
+	} bit;
+};
+
+union syscfg__exticr {
+	u32_t val;
+	struct {
+		u16_t exti;
+		u16_t rsvd__16_31;
+	} bit;
+};
+
+struct stm32f3x_syscfg {
+	union syscfg_cfgr1 cfgr1;
+	union syscfg_rcr rcr;
+	union syscfg__exticr exticr1;
+	union syscfg__exticr exticr2;
+	union syscfg__exticr exticr3;
+	union syscfg__exticr exticr4;
+	u32_t cfgr2;
+	u32_t rsvd_0x1C;
+	u32_t rsvd_0x20;
+	u32_t rsvd_0x24;
+	u32_t rsvd_0x28;
+	u32_t rsvd_0x2C;
+	u32_t rsvd_0x30;
+	u32_t rsvd_0x34;
+	u32_t rsvd_0x38;
+	u32_t rsvd_0x3C;
+	u32_t rsvd_0x40;
+	u32_t rsvd_0x44;
+	u32_t rsvd_0x48;
+	u32_t rsvd_0x4C;
+	u32_t cfgr3;
+};
+
+#endif /* _STM32F3X_GPIO_REGISTERS_H_ */

soc/arm/st_stm32/stm32f3/linker.ld

@@ -0,0 +1,9 @@
+/* linker.ld - Linker command/script file */
+
+/*
+ * Copyright (c) 2014-2016 Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arch/arm/cortex_m/scripts/linker.ld>

soc/arm/st_stm32/stm32f3/soc.c

@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2016 RnDity Sp. z o.o.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for STM32F3 processor
+ */
+
+#include <device.h>
+#include <init.h>
+#include <arch/cpu.h>
+#include <cortex_m/exc.h>
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ * So the init priority has to be 0 (zero).
+ *
+ * @return 0
+ */
+static int stm32f3_init(struct device *arg)
+{
+	u32_t key;
+
+	ARG_UNUSED(arg);
+
+	key = irq_lock();
+
+	_ClearFaults();
+
+	/* Install default handler that simply resets the CPU
+	 * if configured in the kernel, NOP otherwise
+	 */
+	NMI_INIT();
+
+	irq_unlock(key);
+
+	/* Update CMSIS SystemCoreClock variable (HCLK) */
+	/* At reset, system core clock is set to 8 MHz from HSI */
+	SystemCoreClock = 8000000;
+
+	return 0;
+}
+
+SYS_INIT(stm32f3_init, PRE_KERNEL_1, 0);

soc/arm/st_stm32/stm32f3/soc.h

@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2016 RnDity Sp. z o.o.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file SoC configuration macros for the STM32F3 family processors.
+ *
+ * Based on reference manual:
+ *   STM32F303xB/C/D/E, STM32F303x6/8, STM32F328x8, STM32F358xC,
+ *   STM32F398xE advanced ARM(r)-based MCUs
+ *   STM32F37xx advanced ARM(r)-based MCUs
+ *
+ * Chapter 3.3: Memory organization
+ */
+
+
+#ifndef _STM32F3_SOC_H_
+#define _STM32F3_SOC_H_
+
+#define GPIO_REG_SIZE         0x400
+/* base address for where GPIO registers start */
+#define GPIO_PORTS_BASE       (GPIOA_BASE)
+
+#ifndef _ASMLANGUAGE
+
+#include <stm32f3xx.h>
+
+/* ARM CMSIS definitions must be included before kernel_includes.h.
+ * Therefore, it is essential to include kernel_includes.h after including
+ * core SOC-specific headers.
+ */
+#include <kernel_includes.h>
+
+#ifdef CONFIG_SERIAL_HAS_DRIVER
+#include <stm32f3xx_ll_usart.h>
+#endif
+
+#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
+#include <stm32f3xx_ll_utils.h>
+#include <stm32f3xx_ll_bus.h>
+#include <stm32f3xx_ll_rcc.h>
+#include <stm32f3xx_ll_system.h>
+#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
+
+#ifdef CONFIG_I2C
+#include <stm32f3xx_ll_i2c.h>
+#endif
+
+#ifdef CONFIG_SPI_STM32
+#include <stm32f3xx_ll_spi.h>
+#endif
+
+#ifdef CONFIG_IWDG_STM32
+#include <stm32f3xx_ll_iwdg.h>
+#endif
+
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _STM32F3_SOC_H_ */

soc/arm/st_stm32/stm32f3/soc_gpio.c

@@ -0,0 +1,146 @@
+/*
+ * Copyright (c) 2016 RnDity Sp. z o.o.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @brief
+ *
+ * Based on reference manual:
+ *   STM32F303xB/C/D/E, STM32F303x6/8, STM32F328x8, STM32F358xC,
+ *   STM32F398xE advanced ARM ® -based MCUs
+ *
+ * Chapter 11: General-purpose I/Os (GPIO)
+ */
+
+#include <errno.h>
+
+#include <device.h>
+#include "soc.h"
+#include "soc_registers.h"
+#include <gpio.h>
+#include <gpio/gpio_stm32.h>
+
+
+int stm32_gpio_flags_to_conf(int flags, int *pincfg)
+{
+	int direction = flags & GPIO_DIR_MASK;
+	int pud = flags & GPIO_PUD_MASK;
+
+	if (!pincfg) {
+		return -EINVAL;
+	}
+
+	if (direction == GPIO_DIR_OUT) {
+		*pincfg = STM32_MODER_OUTPUT_MODE;
+	} else {
+		/* pull-{up,down} maybe? */
+		*pincfg = STM32_MODER_INPUT_MODE;
+
+		if (pud == GPIO_PUD_PULL_UP) {
+			*pincfg = *pincfg | STM32_PUPDR_PULL_UP;
+		} else if (pud == GPIO_PUD_PULL_DOWN) {
+			*pincfg = *pincfg | STM32_PUPDR_PULL_DOWN;
+		} else {
+			/* floating */
+			*pincfg = *pincfg | STM32_PUPDR_NO_PULL;
+		}
+	}
+
+	return 0;
+}
+
+int stm32_gpio_configure(u32_t *base_addr, int pin, int conf, int altf)
+{
+	volatile struct stm32f3x_gpio *gpio =
+		(struct stm32f3x_gpio *)(base_addr);
+	unsigned int mode, otype, ospeed, pupd;
+	unsigned int pin_shift = pin << 1;
+	unsigned int afr_bank = pin / 8;
+	unsigned int afr_shift = (pin % 8) << 2;
+	u32_t scratch;
+
+	mode = (conf >> STM32_MODER_SHIFT) & STM32_MODER_MASK;
+	otype = (conf >> STM32_OTYPER_SHIFT) & STM32_OTYPER_MASK;
+	ospeed = (conf >> STM32_OSPEEDR_SHIFT) & STM32_OSPEEDR_MASK;
+	pupd = (conf >> STM32_PUPDR_SHIFT) & STM32_PUPDR_MASK;
+
+	scratch = gpio->moder & ~(STM32_MODER_MASK << pin_shift);
+	gpio->moder = scratch | (mode << pin_shift);
+
+	scratch = gpio->ospeedr & ~(STM32_OSPEEDR_MASK << pin_shift);
+	gpio->ospeedr = scratch | (ospeed << pin_shift);
+
+	scratch = gpio->otyper & ~(STM32_OTYPER_MASK << pin);
+	gpio->otyper = scratch | (otype << pin);
+
+	scratch = gpio->pupdr & ~(STM32_PUPDR_MASK << pin_shift);
+	gpio->pupdr = scratch | (pupd << pin_shift);
+
+	scratch = gpio->afr[afr_bank] & ~(STM32_AFR_MASK << afr_shift);
+	gpio->afr[afr_bank] = scratch | (altf << afr_shift);
+
+	return 0;
+}
+
+int stm32_gpio_set(u32_t *base, int pin, int value)
+{
+	struct stm32f3x_gpio *gpio = (struct stm32f3x_gpio *)base;
+
+	int pval = 1 << (pin & 0xf);
+
+	if (value) {
+		gpio->odr |= pval;
+	} else {
+		gpio->odr &= ~pval;
+	}
+
+	return 0;
+}
+
+int stm32_gpio_get(u32_t *base, int pin)
+{
+	struct stm32f3x_gpio *gpio = (struct stm32f3x_gpio *)base;
+
+	return (gpio->idr >> pin) & 0x1;
+}
+
+int stm32_gpio_enable_int(int port, int pin)
+{
+	volatile struct stm32f3x_syscfg *syscfg =
+		(struct stm32f3x_syscfg *)SYSCFG_BASE;
+	volatile union syscfg__exticr *exticr;
+
+	/* Enable System Configuration Controller clock. */
+	struct device *clk =
+		device_get_binding(STM32_CLOCK_CONTROL_NAME);
+
+	struct stm32_pclken pclken = {
+		.bus = STM32_CLOCK_BUS_APB2,
+		.enr = LL_APB2_GRP1_PERIPH_SYSCFG
+	};
+
+	clock_control_on(clk, (clock_control_subsys_t *) &pclken);
+
+	int shift = 0;
+
+	if (pin <= 3) {
+		exticr = &syscfg->exticr1;
+	} else if (pin <= 7) {
+		exticr = &syscfg->exticr2;
+	} else if (pin <= 11) {
+		exticr = &syscfg->exticr3;
+	} else if (pin <= 15) {
+		exticr = &syscfg->exticr4;
+	} else {
+		return -EINVAL;
+	}
+
+	shift = 4 * (pin % 4);
+
+	exticr->val &= ~(0xf << shift);
+	exticr->val |= port << shift;
+
+	return 0;
+}

soc/arm/st_stm32/stm32f3/soc_registers.h

@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2016 RnDity Sp. z o.o.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _STM32F3X_SOC_REGISTERS_H_
+#define _STM32F3X_SOC_REGISTERS_H_
+
+/* include register mapping headers */
+#include "flash_registers.h"
+#include "gpio_registers.h"
+
+#endif /* _STM32F3X_SOC_REGISTERS_H_ */

soc/arm/st_stm32/stm32f4/CMakeLists.txt

@@ -0,0 +1,5 @@
+zephyr_include_directories(${ZEPHYR_BASE}/drivers)
+zephyr_sources(
+  soc.c
+  )
+zephyr_sources_ifdef(CONFIG_GPIO soc_gpio.c)

soc/arm/st_stm32/stm32f4/Kconfig.defconfig.series

@@ -0,0 +1,35 @@
+# Kconfig.defconfig.series - ST Microelectronics STM32F4 MCU line
+#
+# Copyright (c) 2016 Linaro Limited
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_SERIES_STM32F4X
+
+source "soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f4*"
+
+config SOC_SERIES
+	default "stm32f4"
+
+if GPIO_STM32
+
+config GPIO_STM32_PORTD
+	default y
+
+config GPIO_STM32_PORTE
+	default y
+
+config GPIO_STM32_PORTH
+	default y
+
+endif # GPIO_STM32
+
+if I2C_STM32
+
+config I2C_STM32_V1
+	def_bool y
+
+endif # I2C_STM32
+
+endif # SOC_SERIES_STM32F4X

soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f401xe

@@ -0,0 +1,18 @@
+# Kconfig - ST STM32F401RE MCU configuration options
+#
+# Copyright (c) 2016 Linaro Limited.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_STM32F401XE
+
+config SOC
+	string
+	default "stm32f401xe"
+
+config NUM_IRQS
+	int
+	default 85
+
+endif # SOC_STM32F401XE

soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f405xx

@@ -0,0 +1,38 @@
+# Kconfig - ST STM32F405XX MCU configuration options
+#
+# Copyright (c) 2016 Linaro Limited.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_STM32F405XG
+
+config SOC
+	string
+	default "stm32f405xx"
+
+config NUM_IRQS
+	int
+	default 82
+
+if GPIO_STM32
+
+config GPIO_STM32_PORTF
+	default y
+
+config GPIO_STM32_PORTG
+	default y
+
+config GPIO_STM32_PORTI
+	default y
+
+endif # GPIO_STM32
+
+if ENTROPY_GENERATOR
+
+config ENTROPY_STM32_RNG
+	def_bool y
+
+endif # ENTROPY_GENERATOR
+
+endif # SOC_STM32F405XG

soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f407xx

@@ -0,0 +1,38 @@
+# Kconfig - ST STM32F407XX MCU configuration options
+#
+# Copyright (c) 2016 Linaro Limited.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_STM32F407XG
+
+config SOC
+	string
+	default "stm32f407xx"
+
+config NUM_IRQS
+	int
+	default 82
+
+if GPIO_STM32
+
+config GPIO_STM32_PORTF
+	default y
+
+config GPIO_STM32_PORTG
+	default y
+
+config GPIO_STM32_PORTI
+	default y
+
+endif # GPIO_STM32
+
+if ENTROPY_GENERATOR
+
+config ENTROPY_STM32_RNG
+	def_bool y
+
+endif # ENTROPY_GENERATOR
+
+endif # SOC_STM32F407XG

soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f411xe

@@ -0,0 +1,18 @@
+# Kconfig - ST STM32F411CE MCU configuration options
+#
+# Copyright (c) 2016 Linaro Limited.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_STM32F411XE
+
+config SOC
+	string
+	default "stm32f411xe"
+
+config NUM_IRQS
+	int
+	default 86
+
+endif # SOC_STM32F411XE

soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f412cg

@@ -0,0 +1,38 @@
+# Kconfig - ST STM32F412CG MCU configuration options
+#
+# Copyright (c) 2018, I-SENSE group of ICCS
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_STM32F412CG
+
+config SOC
+	string
+	default "stm32f412cx"
+
+config NUM_IRQS
+	int
+	default 97
+
+if GPIO_STM32
+
+config GPIO_STM32_PORTD
+	default n
+
+config GPIO_STM32_PORTE
+	default n
+
+config GPIO_STM32_PORTH
+	default n
+
+endif # GPIO_STM32
+
+if ENTROPY_GENERATOR
+
+config ENTROPY_STM32_RNG
+	def_bool y
+
+endif # ENTROPY_GENERATOR
+
+endif # SOC_STM32F412CG

soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f412zg

@@ -0,0 +1,35 @@
+# Kconfig - ST STM32F412ZG MCU configuration options
+#
+# Copyright (c) 2017 Florian Vaussard, HEIG-VD
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_STM32F412ZG
+
+config SOC
+	string
+	default "stm32f412zx"
+
+config NUM_IRQS
+	int
+	default 97
+
+if GPIO_STM32
+
+config GPIO_STM32_PORTF
+	default y
+
+config GPIO_STM32_PORTG
+	default y
+
+endif # GPIO_STM32
+
+if ENTROPY_GENERATOR
+
+config ENTROPY_STM32_RNG
+	def_bool y
+
+endif # ENTROPY_GENERATOR
+
+endif # SOC_STM32F412ZG

soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f413xx

@@ -0,0 +1,35 @@
+# Kconfig - ST STM32F413XH MCU configuration options
+#
+# Copyright (c) 2017 Florian Vaussard, HEIG-VD
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_STM32F413XH
+
+config SOC
+	string
+	default "stm32f413xx"
+
+config NUM_IRQS
+	int
+	default 102
+
+if GPIO_STM32
+
+config GPIO_STM32_PORTF
+	default y
+
+config GPIO_STM32_PORTG
+	default y
+
+endif # GPIO_STM32
+
+if ENTROPY_GENERATOR
+
+config ENTROPY_STM32_RNG
+	def_bool y
+
+endif # ENTROPY_GENERATOR
+
+endif # SOC_STM32F413XH

soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f417xx

@@ -0,0 +1,38 @@
+# Kconfig - ST STM32F417XX MCU configuration options
+#
+# Copyright (c) 2016 Linaro Limited.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_STM32F417XE || SOC_STM32F417XG
+
+config SOC
+	string
+	default "stm32f417xx"
+
+config NUM_IRQS
+	int
+	default 82
+
+if GPIO_STM32
+
+config GPIO_STM32_PORTF
+	default y
+
+config GPIO_STM32_PORTG
+	default y
+
+config GPIO_STM32_PORTI
+	default y
+
+endif # GPIO_STM32
+
+if ENTROPY_GENERATOR
+
+config ENTROPY_STM32_RNG
+	def_bool y
+
+endif # ENTROPY_GENERATOR
+
+endif # SOC_STM32F417XE || SOC_STM32F417XG

soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f429xx

@@ -0,0 +1,44 @@
+# Kconfig - ST STM32F429XX MCU configuration options
+#
+# Copyright (c) 2016 Linaro Limited.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_STM32F429XI
+
+config SOC
+	string
+	default "stm32f429xx"
+
+config NUM_IRQS
+	int
+	default 91
+
+if GPIO_STM32
+
+config GPIO_STM32_PORTF
+	default y
+
+config GPIO_STM32_PORTG
+	default y
+
+config GPIO_STM32_PORTI
+	default y
+
+config GPIO_STM32_PORTJ
+	default y
+
+config GPIO_STM32_PORTK
+	default y
+
+endif # GPIO_STM32
+
+if ENTROPY_GENERATOR
+
+config ENTROPY_STM32_RNG
+	def_bool y
+
+endif # ENTROPY_GENERATOR
+
+endif # SOC_STM32F429XI

soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f446xe

@@ -0,0 +1,28 @@
+# Kconfig - ST STM32F446XE MCU configuration options
+#
+# Copyright (c) 2018 Philemon Jaermann.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_STM32F446XE
+
+config SOC
+	string
+	default "stm32f446xx"
+
+config NUM_IRQS
+	int
+	default 97
+
+if GPIO_STM32
+
+config GPIO_STM32_PORTE
+	default n
+
+config GPIO_STM32_PORTH
+	default n
+
+endif # GPIO_STM32
+
+endif # SOC_STM32F446XE

soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f469xi

@@ -0,0 +1,44 @@
+# Kconfig - ST STM32F469XI MCU configuration options
+#
+# Copyright (c) 2016 Linaro Limited.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_STM32F469XI
+
+config SOC
+	string
+	default "stm32f469xx"
+
+config NUM_IRQS
+	int
+	default 93
+
+if GPIO_STM32
+
+config GPIO_STM32_PORTF
+	default y
+
+config GPIO_STM32_PORTG
+	default y
+
+config GPIO_STM32_PORTI
+	default y
+
+config GPIO_STM32_PORTJ
+	default y
+
+config GPIO_STM32_PORTK
+	default y
+
+endif # GPIO_STM32
+
+if ENTROPY_GENERATOR
+
+config ENTROPY_STM32_RNG
+	def_bool y
+
+endif # ENTROPY_GENERATOR
+
+endif # SOC_STM32F469XI

soc/arm/st_stm32/stm32f4/Kconfig.series

@@ -0,0 +1,19 @@
+# Kconfig - ST Microelectronics STM32F4 MCU series
+#
+# Copyright (c) 2016 Linaro Limited
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config SOC_SERIES_STM32F4X
+	bool "STM32F4x Series MCU"
+	select CPU_CORTEX_M4
+	select CPU_HAS_FPU
+	select SOC_FAMILY_STM32
+	select SYS_POWER_LOW_POWER_STATE_SUPPORTED
+	select HAS_STM32CUBE
+	select CPU_HAS_MPU
+	select CPU_HAS_SYSTICK
+	select CLOCK_CONTROL_STM32_CUBE if CLOCK_CONTROL
+	help
+	 Enable support for STM32F4 MCU series

soc/arm/st_stm32/stm32f4/Kconfig.soc

@@ -0,0 +1,48 @@
+# Kconfig.soc - ST Microelectronics STM32F4 MCU line
+#
+# Copyright (c) 2016 Linaro Limited.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+choice
+prompt "STM32F4x MCU Selection"
+depends on SOC_SERIES_STM32F4X
+
+config SOC_STM32F401XE
+	bool "STM32F401XE"
+
+config SOC_STM32F405XG
+	bool "STM32F405XG"
+
+config SOC_STM32F407XG
+	bool "STM32F407XG"
+
+config SOC_STM32F411XE
+	bool "STM32F411XE"
+
+config SOC_STM32F412CG
+	bool "STM32F412CG"
+
+config SOC_STM32F412ZG
+	bool "STM32F412ZG"
+
+config SOC_STM32F413XH
+	bool "STM32F413XH"
+
+config SOC_STM32F417XE
+	bool "STM32F417XE"
+
+config SOC_STM32F417XG
+	bool "STM32F417XG"
+
+config SOC_STM32F429XI
+	bool "STM32F429XI"
+
+config SOC_STM32F446XE
+	bool "STM32F446XE"
+
+config SOC_STM32F469XI
+	bool "STM32F469XI"
+
+endchoice

soc/arm/st_stm32/stm32f4/dts.fixup

@@ -0,0 +1,144 @@
+/* SoC level DTS fixup file */
+
+#define CONFIG_NUM_IRQ_PRIO_BITS	        ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
+
+#define CONFIG_UART_STM32_USART_1_BASE_ADDRESS	ST_STM32_USART_40011000_BASE_ADDRESS
+#define CONFIG_UART_STM32_USART_1_BAUD_RATE	ST_STM32_USART_40011000_CURRENT_SPEED
+#define CONFIG_UART_STM32_USART_1_IRQ_PRI	ST_STM32_USART_40011000_IRQ_0_PRIORITY
+#define CONFIG_UART_STM32_USART_1_NAME		ST_STM32_USART_40011000_LABEL
+#define USART_1_IRQ				ST_STM32_USART_40011000_IRQ_0
+
+#define CONFIG_UART_STM32_USART_2_BASE_ADDRESS	ST_STM32_USART_40004400_BASE_ADDRESS
+#define CONFIG_UART_STM32_USART_2_BAUD_RATE	ST_STM32_USART_40004400_CURRENT_SPEED
+#define CONFIG_UART_STM32_USART_2_IRQ_PRI	ST_STM32_USART_40004400_IRQ_0_PRIORITY
+#define CONFIG_UART_STM32_USART_2_NAME		ST_STM32_USART_40004400_LABEL
+#define USART_2_IRQ				ST_STM32_USART_40004400_IRQ_0
+
+#define CONFIG_UART_STM32_USART_3_BASE_ADDRESS   ST_STM32_USART_40004800_BASE_ADDRESS
+#define CONFIG_UART_STM32_USART_3_BAUD_RATE      ST_STM32_USART_40004800_CURRENT_SPEED
+#define CONFIG_UART_STM32_USART_3_IRQ_PRI        ST_STM32_USART_40004800_IRQ_0_PRIORITY
+#define CONFIG_UART_STM32_USART_3_NAME           ST_STM32_USART_40004800_LABEL
+#define USART_3_IRQ                              ST_STM32_USART_40004800_IRQ_0
+
+#define CONFIG_UART_STM32_USART_6_NAME           ST_STM32_USART_40011400_LABEL
+#define CONFIG_UART_STM32_USART_6_BASE_ADDRESS   ST_STM32_USART_40011400_BASE_ADDRESS
+#define CONFIG_UART_STM32_USART_6_BAUD_RATE      ST_STM32_USART_40011400_CURRENT_SPEED
+#define CONFIG_UART_STM32_USART_6_IRQ_PRI        ST_STM32_USART_40011400_IRQ_0_PRIORITY
+#define USART_6_IRQ                              ST_STM32_USART_40011400_IRQ_0
+
+#define CONFIG_I2C_1_BASE_ADDRESS               ST_STM32_I2C_V1_40005400_BASE_ADDRESS
+#define CONFIG_I2C_1_EVENT_IRQ_PRI              ST_STM32_I2C_V1_40005400_IRQ_EVENT_PRIORITY
+#define CONFIG_I2C_1_ERROR_IRQ_PRI              ST_STM32_I2C_V1_40005400_IRQ_ERROR_PRIORITY
+#define CONFIG_I2C_1_NAME                       ST_STM32_I2C_V1_40005400_LABEL
+#define CONFIG_I2C_1_EVENT_IRQ                  ST_STM32_I2C_V1_40005400_IRQ_EVENT
+#define CONFIG_I2C_1_ERROR_IRQ                  ST_STM32_I2C_V1_40005400_IRQ_ERROR
+#define CONFIG_I2C_1_BITRATE                    ST_STM32_I2C_V1_40005400_CLOCK_FREQUENCY
+
+#define CONFIG_I2C_2_BASE_ADDRESS               ST_STM32_I2C_V1_40005800_BASE_ADDRESS
+#define CONFIG_I2C_2_EVENT_IRQ_PRI              ST_STM32_I2C_V1_40005800_IRQ_EVENT_PRIORITY
+#define CONFIG_I2C_2_ERROR_IRQ_PRI              ST_STM32_I2C_V1_40005800_IRQ_ERROR_PRIORITY
+#define CONFIG_I2C_2_NAME                       ST_STM32_I2C_V1_40005800_LABEL
+#define CONFIG_I2C_2_EVENT_IRQ                  ST_STM32_I2C_V1_40005800_IRQ_EVENT
+#define CONFIG_I2C_2_ERROR_IRQ                  ST_STM32_I2C_V1_40005800_IRQ_ERROR
+#define CONFIG_I2C_2_BITRATE                    ST_STM32_I2C_V1_40005800_CLOCK_FREQUENCY
+
+#define CONFIG_I2C_3_BASE_ADDRESS               ST_STM32_I2C_V1_40005C00_BASE_ADDRESS
+#define CONFIG_I2C_3_EVENT_IRQ_PRI              ST_STM32_I2C_V1_40005C00_IRQ_EVENT_PRIORITY
+#define CONFIG_I2C_3_ERROR_IRQ_PRI              ST_STM32_I2C_V1_40005C00_IRQ_ERROR_PRIORITY
+#define CONFIG_I2C_3_NAME                       ST_STM32_I2C_V1_40005C00_LABEL
+#define CONFIG_I2C_3_EVENT_IRQ                  ST_STM32_I2C_V1_40005C00_IRQ_EVENT
+#define CONFIG_I2C_3_ERROR_IRQ                  ST_STM32_I2C_V1_40005C00_IRQ_ERROR
+#define CONFIG_I2C_3_BITRATE                    ST_STM32_I2C_V1_40005C00_CLOCK_FREQUENCY
+
+#define CONFIG_SPI_1_BASE_ADDRESS               ST_STM32_SPI_40013000_BASE_ADDRESS
+#define CONFIG_SPI_1_IRQ_PRI                    ST_STM32_SPI_40013000_IRQ_0_PRIORITY
+#define CONFIG_SPI_1_NAME                       ST_STM32_SPI_40013000_LABEL
+#define CONFIG_SPI_1_IRQ                        ST_STM32_SPI_40013000_IRQ_0
+
+#define CONFIG_SPI_2_BASE_ADDRESS               ST_STM32_SPI_40003800_BASE_ADDRESS
+#define CONFIG_SPI_2_IRQ_PRI                    ST_STM32_SPI_40003800_IRQ_0_PRIORITY
+#define CONFIG_SPI_2_NAME                       ST_STM32_SPI_40003800_LABEL
+#define CONFIG_SPI_2_IRQ                        ST_STM32_SPI_40003800_IRQ_0
+
+#define CONFIG_SPI_3_BASE_ADDRESS		ST_STM32_SPI_40003C00_BASE_ADDRESS
+#define CONFIG_SPI_3_IRQ_PRI			ST_STM32_SPI_40003C00_IRQ_0_PRIORITY
+#define CONFIG_SPI_3_NAME			ST_STM32_SPI_40003C00_LABEL
+#define CONFIG_SPI_3_IRQ			ST_STM32_SPI_40003C00_IRQ_0
+
+#define CONFIG_SPI_4_BASE_ADDRESS		ST_STM32_SPI_40013400_BASE_ADDRESS
+#define CONFIG_SPI_4_IRQ_PRI			ST_STM32_SPI_40013400_IRQ_0_PRIORITY
+#define CONFIG_SPI_4_NAME			ST_STM32_SPI_40013400_LABEL
+#define CONFIG_SPI_4_IRQ			ST_STM32_SPI_40013400_IRQ_0
+
+#define CONFIG_SPI_5_BASE_ADDRESS		ST_STM32_SPI_40015000_BASE_ADDRESS
+#define CONFIG_SPI_5_IRQ_PRI			ST_STM32_SPI_40015000_IRQ_0_PRIORITY
+#define CONFIG_SPI_5_NAME			ST_STM32_SPI_40015000_LABEL
+#define CONFIG_SPI_5_IRQ			ST_STM32_SPI_40015000_IRQ_0
+
+#define CONFIG_SPI_6_BASE_ADDRESS		ST_STM32_SPI_40015400_BASE_ADDRESS
+#define CONFIG_SPI_6_IRQ_PRI			ST_STM32_SPI_40015400_IRQ_0_PRIORITY
+#define CONFIG_SPI_6_NAME			ST_STM32_SPI_40015400_LABEL
+#define CONFIG_SPI_6_IRQ			ST_STM32_SPI_40015400_IRQ_0
+
+#define FLASH_DEV_BASE_ADDRESS		        ST_STM32F4_FLASH_CONTROLLER_40023C00_BASE_ADDRESS
+#define FLASH_DEV_NAME			        ST_STM32F4_FLASH_CONTROLLER_40023C00_LABEL
+
+#ifdef ST_STM32_OTGFS_50000000_BASE_ADDRESS
+#define CONFIG_USB_BASE_ADDRESS			ST_STM32_OTGFS_50000000_BASE_ADDRESS
+#define CONFIG_USB_IRQ				ST_STM32_OTGFS_50000000_IRQ_OTGFS
+#define CONFIG_USB_IRQ_PRI			ST_STM32_OTGFS_50000000_IRQ_OTGFS_PRIORITY
+#define CONFIG_USB_NUM_BIDIR_ENDPOINTS		ST_STM32_OTGFS_50000000_NUM_BIDIR_ENDPOINTS
+#define CONFIG_USB_RAM_SIZE			ST_STM32_OTGFS_50000000_RAM_SIZE
+#endif /*  ST_STM32_OTGFS_50000000_BASE_ADDRESS */
+
+#ifdef ST_STM32_OTGHS_40040000_BASE_ADDRESS
+#define CONFIG_USB_HS_BASE_ADDRESS		ST_STM32_OTGHS_40040000_BASE_ADDRESS
+#define CONFIG_USB_IRQ				ST_STM32_OTGHS_40040000_IRQ_OTGHS
+#define CONFIG_USB_IRQ_PRI			ST_STM32_OTGHS_40040000_IRQ_OTGHS_PRIORITY
+#define CONFIG_USB_NUM_BIDIR_ENDPOINTS		ST_STM32_OTGHS_40040000_NUM_BIDIR_ENDPOINTS
+#define CONFIG_USB_RAM_SIZE			ST_STM32_OTGHS_40040000_RAM_SIZE
+#endif /* ST_STM32_OTGHS_40040000_BASE_ADDRESS */
+
+#define CONFIG_PWM_STM32_1_DEV_NAME             ST_STM32_PWM_40010000_PWM_LABEL
+#define CONFIG_PWM_STM32_1_PRESCALER            ST_STM32_PWM_40010000_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_2_DEV_NAME             ST_STM32_PWM_40000000_PWM_LABEL
+#define CONFIG_PWM_STM32_2_PRESCALER            ST_STM32_PWM_40000000_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_3_DEV_NAME             ST_STM32_PWM_40000400_PWM_LABEL
+#define CONFIG_PWM_STM32_3_PRESCALER            ST_STM32_PWM_40000400_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_4_DEV_NAME             ST_STM32_PWM_40000800_PWM_LABEL
+#define CONFIG_PWM_STM32_4_PRESCALER            ST_STM32_PWM_40000800_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_5_DEV_NAME             ST_STM32_PWM_40000C00_PWM_LABEL
+#define CONFIG_PWM_STM32_5_PRESCALER            ST_STM32_PWM_40000C00_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_6_DEV_NAME             ST_STM32_PWM_40001000_PWM_LABEL
+#define CONFIG_PWM_STM32_6_PRESCALER            ST_STM32_PWM_40001000_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_7_DEV_NAME             ST_STM32_PWM_40001400_PWM_LABEL
+#define CONFIG_PWM_STM32_7_PRESCALER            ST_STM32_PWM_40001400_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_8_DEV_NAME             ST_STM32_PWM_40010400_PWM_LABEL
+#define CONFIG_PWM_STM32_8_PRESCALER            ST_STM32_PWM_40010400_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_9_DEV_NAME             ST_STM32_PWM_40014000_PWM_LABEL
+#define CONFIG_PWM_STM32_9_PRESCALER            ST_STM32_PWM_40014000_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_10_DEV_NAME            ST_STM32_PWM_40014400_PWM_LABEL
+#define CONFIG_PWM_STM32_10_PRESCALER           ST_STM32_PWM_40014400_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_11_DEV_NAME            ST_STM32_PWM_40014800_PWM_LABEL
+#define CONFIG_PWM_STM32_11_PRESCALER           ST_STM32_PWM_40014800_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_12_DEV_NAME            ST_STM32_PWM_40001800_PWM_LABEL
+#define CONFIG_PWM_STM32_12_PRESCALER           ST_STM32_PWM_40001800_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_13_DEV_NAME            ST_STM32_PWM_40001C00_PWM_LABEL
+#define CONFIG_PWM_STM32_13_PRESCALER           ST_STM32_PWM_40001C00_PWM_ST_PRESCALER
+
+#define CONFIG_PWM_STM32_14_DEV_NAME            ST_STM32_PWM_40002000_PWM_LABEL
+#define CONFIG_PWM_STM32_14_PRESCALER           ST_STM32_PWM_40002000_PWM_ST_PRESCALER
+
+/* End of SoC Level DTS fixup file */

soc/arm/st_stm32/stm32f4/flash_registers.h

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2016 Linaro Limited.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _STM32F4X_FLASH_REGISTERS_H_
+#define _STM32F4X_FLASH_REGISTERS_H_
+
+/**
+ * @brief
+ *
+ * Based on reference manual:
+ *
+ * Chapter 3.4: Embedded Flash Memory
+ */
+
+union __flash_acr {
+	u32_t val;
+	struct {
+		u32_t latency :4 __packed;
+		u32_t rsvd__4_7 :4 __packed;
+		u32_t prften :1 __packed;
+		u32_t icen :1 __packed;
+		u32_t dcen :1 __packed;
+		u32_t icrst :1 __packed;
+		u32_t dcrst :1 __packed;
+		u32_t rsvd__13_31 :19 __packed;
+	} bit;
+};
+
+/* 3.8.7 Embedded flash registers */
+struct stm32f4x_flash {
+	volatile union __flash_acr acr;
+	volatile u32_t keyr;
+	volatile u32_t optkeyr;
+	volatile u32_t sr;
+	volatile u32_t cr;
+	volatile u32_t optcr;
+};
+
+#endif	/* _STM32F4X_FLASHREGISTERS_H_ */

soc/arm/st_stm32/stm32f4/gpio_registers.h

@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2016 Linaro Limited.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _STM32F4X_GPIO_REGISTERS_H_
+#define _STM32F4X_GPIO_REGISTERS_H_
+
+/**
+ * @brief Driver for GPIO of STM32F4X family processor.
+ *
+ * Based on reference manual:
+ *   RM0368 Reference manual STM32F401xB/C and STM32F401xD/E
+ *   advanced ARM(r)-based 32-bit MCUs
+ *
+ * Chapter 8: General-purpose I/Os (GPIOs)
+ */
+
+/* 8.4 GPIO registers - each GPIO port controls 16 pins */
+struct stm32f4x_gpio {
+	u32_t mode;
+	u32_t otype;
+	u32_t ospeed;
+	u32_t pupdr;
+	u32_t idr;
+	u32_t odr;
+	u32_t bsr;
+	u32_t lck;
+	u32_t afr[2];
+};
+
+union syscfg_exticr {
+	u32_t val;
+	struct {
+		u16_t rsvd__16_31;
+		u16_t exti;
+	} bit;
+};
+
+/* 7.2 SYSCFG registers */
+struct stm32f4x_syscfg {
+	u32_t memrmp;
+	u32_t pmc;
+	union syscfg_exticr exticr1;
+	union syscfg_exticr exticr2;
+	union syscfg_exticr exticr3;
+	union syscfg_exticr exticr4;
+	u32_t cmpcr;
+};
+
+#endif /* _STM32F4X_GPIO_REGISTERS_H_ */

soc/arm/st_stm32/stm32f4/linker.ld

@@ -0,0 +1,9 @@
+/* linker.ld - Linker command/script file */
+
+/*
+ * Copyright (c) 2014-2016 Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arch/arm/cortex_m/scripts/linker.ld>

soc/arm/st_stm32/stm32f4/soc.c

@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2016 Open-RnD Sp. z o.o.
+ * Copyright (c) 2016 Linaro Limited.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for STM32F4 processor
+ */
+
+#include <device.h>
+#include <init.h>
+#include <arch/cpu.h>
+#include <cortex_m/exc.h>
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ * So the init priority has to be 0 (zero).
+ *
+ * @return 0
+ */
+static int st_stm32f4_init(struct device *arg)
+{
+	u32_t key;
+
+	ARG_UNUSED(arg);
+
+	key = irq_lock();
+
+	_ClearFaults();
+
+	/* Install default handler that simply resets the CPU
+	 * if configured in the kernel, NOP otherwise
+	 */
+	NMI_INIT();
+
+	irq_unlock(key);
+
+	/* Update CMSIS SystemCoreClock variable (HCLK) */
+	/* At reset, system core clock is set to 16 MHz from HSI */
+	SystemCoreClock = 16000000;
+
+	return 0;
+}
+
+SYS_INIT(st_stm32f4_init, PRE_KERNEL_1, 0);

soc/arm/st_stm32/stm32f4/soc.h

@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2016 Open-RnD Sp. z o.o.
+ * Copyright (c) 2016 Linaro Limited.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file SoC configuration macros for the ST STM32F4 family processors.
+ *
+ * Based on reference manual:
+ *   RM0368 Reference manual STM32F401xB/C and STM32F401xD/E
+ *   advanced ARM(r)-based 32-bit MCUs
+ *
+ * Chapter 2.3: Memory Map
+ */
+
+#ifndef _STM32F4_SOC_H_
+#define _STM32F4_SOC_H_
+
+#define GPIO_REG_SIZE         0x400
+/* base address for where GPIO registers start */
+#define GPIO_PORTS_BASE       (GPIOA_BASE)
+
+#ifndef _ASMLANGUAGE
+
+#include <stm32f4xx.h>
+
+/* ARM CMSIS definitions must be included before kernel_includes.h.
+ * Therefore, it is essential to include kernel_includes.h after including
+ * core SOC-specific headers.
+ */
+#include <kernel_includes.h>
+
+#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
+#include <stm32f4xx_ll_utils.h>
+#include <stm32f4xx_ll_bus.h>
+#include <stm32f4xx_ll_rcc.h>
+#include <stm32f4xx_ll_system.h>
+#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
+
+#ifdef CONFIG_SERIAL_HAS_DRIVER
+#include <stm32f4xx_ll_usart.h>
+#endif
+
+#ifdef CONFIG_I2C
+#include <stm32f4xx_ll_i2c.h>
+#endif
+
+#ifdef CONFIG_SPI_STM32
+#include <stm32f4xx_ll_spi.h>
+#endif
+
+#ifdef CONFIG_ENTROPY_STM32_RNG
+#include <stm32f4xx_ll_rng.h>
+#endif
+
+#ifdef CONFIG_IWDG_STM32
+#include <stm32f4xx_ll_iwdg.h>
+#endif
+
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _STM32F4_SOC_H_ */

soc/arm/st_stm32/stm32f4/soc_gpio.c

@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) Linaro Limited.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @brief
+ *
+ * Based on reference manual:
+ *   RM0368 Reference manual STM32F401xB/C and STM32F401xD/E
+ *   advanced ARM ® -based 32-bit MCUs
+ *
+ * Chapter 8: General-purpose I/Os (GPIOs)
+ */
+
+#include <errno.h>
+
+#include <device.h>
+#include "soc.h"
+#include "soc_registers.h"
+#include <gpio.h>
+#include <gpio/gpio_stm32.h>
+
+
+int stm32_gpio_flags_to_conf(int flags, int *pincfg)
+{
+	int direction = flags & GPIO_DIR_MASK;
+	int pud = flags & GPIO_PUD_MASK;
+
+	if (!pincfg) {
+		return -EINVAL;
+	}
+
+	if (direction == GPIO_DIR_OUT) {
+		*pincfg = STM32_MODER_OUTPUT_MODE;
+	} else {
+		/* pull-{up,down} maybe? */
+		*pincfg = STM32_MODER_INPUT_MODE;
+
+		if (pud == GPIO_PUD_PULL_UP) {
+			*pincfg = *pincfg | STM32_PUPDR_PULL_UP;
+		} else if (pud == GPIO_PUD_PULL_DOWN) {
+			*pincfg = *pincfg | STM32_PUPDR_PULL_DOWN;
+		} else {
+			/* floating */
+			*pincfg = *pincfg | STM32_PUPDR_NO_PULL;
+		}
+	}
+
+	return 0;
+}
+
+int stm32_gpio_configure(u32_t *base_addr, int pin, int conf, int altf)
+{
+	volatile struct stm32f4x_gpio *gpio =
+		(struct stm32f4x_gpio *)(base_addr);
+	unsigned int mode, otype, ospeed, pupd;
+	unsigned int pin_shift = pin << 1;
+	unsigned int afr_bank = pin / 8;
+	unsigned int afr_shift = (pin % 8) << 2;
+	u32_t scratch;
+
+	mode = (conf >> STM32_MODER_SHIFT) & STM32_MODER_MASK;
+	otype = (conf >> STM32_OTYPER_SHIFT) & STM32_OTYPER_MASK;
+	ospeed = (conf >> STM32_OSPEEDR_SHIFT) & STM32_OSPEEDR_MASK;
+	pupd = (conf >> STM32_PUPDR_SHIFT) & STM32_PUPDR_MASK;
+
+	scratch = gpio->mode & ~(STM32_MODER_MASK << pin_shift);
+	gpio->mode = scratch | (mode << pin_shift);
+
+	scratch = gpio->ospeed & ~(STM32_OSPEEDR_MASK << pin_shift);
+	gpio->ospeed = scratch | (ospeed << pin_shift);
+
+	scratch = gpio->otype & ~(STM32_OTYPER_MASK << pin);
+	gpio->otype = scratch | (otype << pin);
+
+	scratch = gpio->pupdr & ~(STM32_PUPDR_MASK << pin_shift);
+	gpio->pupdr = scratch | (pupd << pin_shift);
+
+	scratch = gpio->afr[afr_bank] & ~(STM32_AFR_MASK << afr_shift);
+	gpio->afr[afr_bank] = scratch | (altf << afr_shift);
+
+	return 0;
+}
+
+int stm32_gpio_set(u32_t *base, int pin, int value)
+{
+	struct stm32f4x_gpio *gpio = (struct stm32f4x_gpio *)base;
+
+	if (value) {
+		/* atomic set */
+		gpio->bsr = (1 << (pin & 0x0f));
+	} else {
+		/* atomic reset */
+		gpio->bsr = (1 << ((pin & 0x0f) + 0x10));
+	}
+
+	return 0;
+}
+
+int stm32_gpio_get(u32_t *base, int pin)
+{
+	struct stm32f4x_gpio *gpio = (struct stm32f4x_gpio *)base;
+
+	return (gpio->idr >> pin) & 0x1;
+}
+
+int stm32_gpio_enable_int(int port, int pin)
+{
+	volatile struct stm32f4x_syscfg *syscfg =
+		(struct stm32f4x_syscfg *)SYSCFG_BASE;
+	volatile union syscfg_exticr *exticr;
+	struct device *clk = device_get_binding(STM32_CLOCK_CONTROL_NAME);
+	struct stm32_pclken pclken = {
+		.bus = STM32_CLOCK_BUS_APB2,
+		.enr = LL_APB2_GRP1_PERIPH_SYSCFG
+	};
+	int shift = 0;
+
+	/* Enable SYSCFG clock */
+	clock_control_on(clk, (clock_control_subsys_t *) &pclken);
+
+	if (pin <= 3) {
+		exticr = &syscfg->exticr1;
+	} else if (pin <= 7) {
+		exticr = &syscfg->exticr2;
+	} else if (pin <= 11) {
+		exticr = &syscfg->exticr3;
+	} else if (pin <= 15) {
+		exticr = &syscfg->exticr4;
+	} else {
+		return -EINVAL;
+	}
+
+	shift = 4 * (pin % 4);
+
+	exticr->val &= ~(0xf << shift);
+	exticr->val |= port << shift;
+
+	return 0;
+}

soc/arm/st_stm32/stm32f4/soc_registers.h

@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2016 Linaro Limited.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _STM32F4_SOC_REGISTERS_H_
+#define _STM32F4_SOC_REGISTERS_H_
+
+/* include register mapping headers */
+#include "flash_registers.h"
+#include "gpio_registers.h"
+
+#endif /* _STM32F4_SOC_REGISTERS_H_ */

soc/arm/st_stm32/stm32f7/CMakeLists.txt

@@ -0,0 +1,5 @@
+zephyr_include_directories(${ZEPHYR_BASE}/drivers)
+zephyr_sources(
+  soc.c
+  )
+zephyr_sources_ifdef(CONFIG_GPIO soc_gpio.c)

soc/arm/st_stm32/stm32f7/Kconfig.defconfig.series

@@ -0,0 +1,45 @@
+# Kconfig.defconfig.series - ST Microelectronics STM32F7 MCU line
+#
+# Copyright (c) 2018 Yurii Hamann
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_SERIES_STM32F7X
+
+source "soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f7*"
+
+config SOC_SERIES
+	default "stm32f7"
+
+if GPIO_STM32
+
+config GPIO_STM32_PORTD
+	default y
+
+config GPIO_STM32_PORTE
+	default y
+
+config GPIO_STM32_PORTH
+	default y
+
+config GPIO_STM32_PORTI
+	default y
+
+endif # GPIO_STM32
+
+if I2C_STM32
+
+config I2C_STM32_V2
+	def_bool y
+
+endif # I2C_STM32
+
+if ENTROPY_GENERATOR
+
+config ENTROPY_STM32_RNG
+	def_bool y
+
+endif # ENTROPY_GENERATOR
+
+endif # SOC_SERIES_STM32F7X

soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f723xe

@@ -0,0 +1,18 @@
+# Kconfig - ST STM32F723XE MCU configuration options
+#
+# Copyright (c) 2018 Aurelien Jarno
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_STM32F723XE
+
+config SOC
+	string
+	default "stm32f723xx"
+
+config NUM_IRQS
+	int
+	default 104
+
+endif # SOC_STM32F723XE

soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f746xg

@@ -0,0 +1,28 @@
+# Kconfig - ST STM32F746XG MCU configuration options
+#
+# Copyright (c) 2018 Yurii Hamann
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_STM32F746XG
+
+config SOC
+	string
+	default "stm32f746xx"
+
+if GPIO_STM32
+
+config GPIO_STM32_PORTJ
+	default y
+
+config GPIO_STM32_PORTK
+	default y
+
+endif # GPIO_STM32
+
+config NUM_IRQS
+	int
+	default 98
+
+endif # SOC_STM32F746XG

soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f769xi

@@ -0,0 +1,28 @@
+# Kconfig - ST STM32F769XI MCU configuration options
+#
+# Copyright (c) 2018  Yong Jin
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_STM32F769XI
+
+config SOC
+	string
+	default "stm32f769xx"
+
+if GPIO_STM32
+
+config GPIO_STM32_PORTJ
+	default y
+
+config GPIO_STM32_PORTK
+	default y
+
+endif # GPIO_STM32
+
+config NUM_IRQS
+	int
+	default 110
+
+endif # SOC_STM32F769XI

soc/arm/st_stm32/stm32f7/Kconfig.series

@@ -0,0 +1,18 @@
+# Kconfig - ST Microelectronics STM32F7 MCU series
+#
+# Copyright (c) 2018 Yurii Hamann
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config SOC_SERIES_STM32F7X
+	bool "STM32F7x Series MCU"
+	select CPU_CORTEX_M7
+	select CPU_HAS_FPU
+	select SOC_FAMILY_STM32
+	select SYS_POWER_LOW_POWER_STATE_SUPPORTED
+	select HAS_STM32CUBE
+	select CPU_HAS_SYSTICK
+	select CLOCK_CONTROL_STM32_CUBE if CLOCK_CONTROL
+	help
+	 Enable support for STM32F7 MCU series

soc/arm/st_stm32/stm32f7/Kconfig.soc

@@ -0,0 +1,21 @@
+# Kconfig.soc - ST Microelectronics STM32F7 MCU line
+#
+# Copyright (c) 2018 Yurii Hamann
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+choice
+prompt "STM32F7x MCU Selection"
+depends on SOC_SERIES_STM32F7X
+
+config SOC_STM32F723XE
+	bool "STM32F723XE"
+
+config SOC_STM32F746XG
+	bool "STM32F746XG"
+
+config SOC_STM32F769XI
+	bool "STM32F769XI"
+
+endchoice

soc/arm/st_stm32/stm32f7/dts.fixup

@@ -0,0 +1,93 @@
+/* SoC level DTS fixup file */
+
+#define CONFIG_NUM_IRQ_PRIO_BITS		ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
+
+#define CONFIG_UART_STM32_USART_1_BASE_ADDRESS	ST_STM32_USART_40011000_BASE_ADDRESS
+#define CONFIG_UART_STM32_USART_1_BAUD_RATE	ST_STM32_USART_40011000_CURRENT_SPEED
+#define CONFIG_UART_STM32_USART_1_IRQ_PRI	ST_STM32_USART_40011000_IRQ_0_PRIORITY
+#define CONFIG_UART_STM32_USART_1_NAME		ST_STM32_USART_40011000_LABEL
+#define USART_1_IRQ				ST_STM32_USART_40011000_IRQ_0
+
+#define CONFIG_UART_STM32_USART_2_BASE_ADDRESS	ST_STM32_USART_40004400_BASE_ADDRESS
+#define CONFIG_UART_STM32_USART_2_BAUD_RATE	ST_STM32_USART_40004400_CURRENT_SPEED
+#define CONFIG_UART_STM32_USART_2_IRQ_PRI	ST_STM32_USART_40004400_IRQ_0_PRIORITY
+#define CONFIG_UART_STM32_USART_2_NAME		ST_STM32_USART_40004400_LABEL
+#define USART_2_IRQ				ST_STM32_USART_40004400_IRQ_0
+
+#define CONFIG_UART_STM32_USART_3_BASE_ADDRESS	ST_STM32_USART_40004800_BASE_ADDRESS
+#define CONFIG_UART_STM32_USART_3_BAUD_RATE	ST_STM32_USART_40004800_CURRENT_SPEED
+#define CONFIG_UART_STM32_USART_3_IRQ_PRI	ST_STM32_USART_40004800_IRQ_0_PRIORITY
+#define CONFIG_UART_STM32_USART_3_NAME		ST_STM32_USART_40004800_LABEL
+#define USART_3_IRQ				ST_STM32_USART_40004800_IRQ_0
+
+#define CONFIG_UART_STM32_USART_4_BASE_ADDRESS	ST_STM32_USART_40004C00_BASE_ADDRESS
+#define CONFIG_UART_STM32_USART_4_BAUD_RATE	ST_STM32_USART_40004C00_CURRENT_SPEED
+#define CONFIG_UART_STM32_USART_4_IRQ_PRI	ST_STM32_USART_40004C00_IRQ_0_PRIORITY
+#define CONFIG_UART_STM32_USART_4_NAME		ST_STM32_USART_40004C00_LABEL
+#define USART_4_IRQ				ST_STM32_USART_40004C00_IRQ_0
+
+#define CONFIG_UART_STM32_USART_5_BASE_ADDRESS	ST_STM32_USART_40005000_BASE_ADDRESS
+#define CONFIG_UART_STM32_USART_5_BAUD_RATE	ST_STM32_USART_40005000_CURRENT_SPEED
+#define CONFIG_UART_STM32_USART_5_IRQ_PRI	ST_STM32_USART_40005000_IRQ_0_PRIORITY
+#define CONFIG_UART_STM32_USART_5_NAME		ST_STM32_USART_40005000_LABEL
+#define USART_5_IRQ				ST_STM32_USART_40005000_IRQ_0
+
+#define CONFIG_UART_STM32_USART_6_BASE_ADDRESS	ST_STM32_USART_40011400_BASE_ADDRESS
+#define CONFIG_UART_STM32_USART_6_BAUD_RATE	ST_STM32_USART_40011400_CURRENT_SPEED
+#define CONFIG_UART_STM32_USART_6_IRQ_PRI	ST_STM32_USART_40011400_IRQ_0_PRIORITY
+#define CONFIG_UART_STM32_USART_6_NAME		ST_STM32_USART_40011400_LABEL
+#define USART_6_IRQ				ST_STM32_USART_40011400_IRQ_0
+
+#define CONFIG_UART_STM32_USART_7_BASE_ADDRESS	ST_STM32_USART_40007800_BASE_ADDRESS
+#define CONFIG_UART_STM32_USART_7_BAUD_RATE	ST_STM32_USART_40007800_CURRENT_SPEED
+#define CONFIG_UART_STM32_USART_7_IRQ_PRI	ST_STM32_USART_40007800_IRQ_0_PRIORITY
+#define CONFIG_UART_STM32_USART_7_NAME		ST_STM32_USART_40007800_LABEL
+#define USART_7_IRQ				ST_STM32_USART_40007800_IRQ_0
+
+#define CONFIG_UART_STM32_USART_8_BASE_ADDRESS	ST_STM32_USART_40007C00_BASE_ADDRESS
+#define CONFIG_UART_STM32_USART_8_BAUD_RATE	ST_STM32_USART_40007C00_CURRENT_SPEED
+#define CONFIG_UART_STM32_USART_8_IRQ_PRI	ST_STM32_USART_40007C00_IRQ_0_PRIORITY
+#define CONFIG_UART_STM32_USART_8_NAME		ST_STM32_USART_40007800_LABEL
+#define USART_8_IRQ				ST_STM32_USART_40007C00_IRQ_0
+
+#define CONFIG_I2C_1_BASE_ADDRESS		ST_STM32_I2C_V2_40005400_BASE_ADDRESS
+#define CONFIG_I2C_1_EVENT_IRQ_PRI		ST_STM32_I2C_V2_40005400_IRQ_EVENT_PRIORITY
+#define CONFIG_I2C_1_ERROR_IRQ_PRI		ST_STM32_I2C_V2_40005400_IRQ_ERROR_PRIORITY
+#define CONFIG_I2C_1_NAME			ST_STM32_I2C_V2_40005400_LABEL
+#define CONFIG_I2C_1_EVENT_IRQ			ST_STM32_I2C_V2_40005400_IRQ_EVENT
+#define CONFIG_I2C_1_ERROR_IRQ			ST_STM32_I2C_V2_40005400_IRQ_ERROR
+#define CONFIG_I2C_1_BITRATE			ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY
+
+#define CONFIG_I2C_2_BASE_ADDRESS		ST_STM32_I2C_V2_40005800_BASE_ADDRESS
+#define CONFIG_I2C_2_EVENT_IRQ_PRI		ST_STM32_I2C_V2_40005800_IRQ_EVENT_PRIORITY
+#define CONFIG_I2C_2_ERROR_IRQ_PRI		ST_STM32_I2C_V2_40005800_IRQ_ERROR_PRIORITY
+#define CONFIG_I2C_2_NAME			ST_STM32_I2C_V2_40005800_LABEL
+#define CONFIG_I2C_2_EVENT_IRQ			ST_STM32_I2C_V2_40005800_IRQ_EVENT
+#define CONFIG_I2C_2_ERROR_IRQ			ST_STM32_I2C_V2_40005800_IRQ_ERROR
+#define CONFIG_I2C_2_BITRATE			ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY
+
+#define CONFIG_I2C_3_BASE_ADDRESS		ST_STM32_I2C_V2_40005C00_BASE_ADDRESS
+#define CONFIG_I2C_3_EVENT_IRQ_PRI		ST_STM32_I2C_V2_40005C00_IRQ_EVENT_PRIORITY
+#define CONFIG_I2C_3_ERROR_IRQ_PRI		ST_STM32_I2C_V2_40005C00_IRQ_ERROR_PRIORITY
+#define CONFIG_I2C_3_NAME			ST_STM32_I2C_V2_40005C00_LABEL
+#define CONFIG_I2C_3_EVENT_IRQ			ST_STM32_I2C_V2_40005C00_IRQ_EVENT
+#define CONFIG_I2C_3_ERROR_IRQ			ST_STM32_I2C_V2_40005C00_IRQ_ERROR
+#define CONFIG_I2C_3_BITRATE			ST_STM32_I2C_V2_40005C00_CLOCK_FREQUENCY
+
+#ifdef ST_STM32_OTGFS_50000000_BASE_ADDRESS
+#define CONFIG_USB_BASE_ADDRESS			ST_STM32_OTGFS_50000000_BASE_ADDRESS
+#define CONFIG_USB_IRQ				ST_STM32_OTGFS_50000000_IRQ_OTGFS
+#define CONFIG_USB_IRQ_PRI			ST_STM32_OTGFS_50000000_IRQ_OTGFS_PRIORITY
+#define CONFIG_USB_NUM_BIDIR_ENDPOINTS		ST_STM32_OTGFS_50000000_NUM_BIDIR_ENDPOINTS
+#define CONFIG_USB_RAM_SIZE			ST_STM32_OTGFS_50000000_RAM_SIZE
+#endif /* ST_STM32_OTGFS_50000000_BASE_ADDRESS */
+
+#ifdef ST_STM32_OTGHS_40040000_BASE_ADDRESS
+#define CONFIG_USB_HS_BASE_ADDRESS		ST_STM32_OTGHS_40040000_BASE_ADDRESS
+#define CONFIG_USB_IRQ				ST_STM32_OTGHS_40040000_IRQ_OTGHS
+#define CONFIG_USB_IRQ_PRI			ST_STM32_OTGHS_40040000_IRQ_OTGHS_PRIORITY
+#define CONFIG_USB_NUM_BIDIR_ENDPOINTS		ST_STM32_OTGHS_40040000_NUM_BIDIR_ENDPOINTS
+#define CONFIG_USB_RAM_SIZE			ST_STM32_OTGHS_40040000_RAM_SIZE
+#endif /* ST_STM32_OTGHS_40040000_BASE_ADDRESS */
+
+/* End of SoC Level DTS fixup file */

soc/arm/st_stm32/stm32f7/flash_registers.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2018 Yurii Hamann
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _STM32F7X_FLASH_REGISTERS_H_
+#define _STM32F7X_FLASH_REGISTERS_H_
+
+/**
+ * @brief
+ *
+ * Based on reference manual:
+ *   RM0385 Reference manual STM32F75xxx and STM32F74xxx
+ *   advanced ARM(r)-based 32-bit MCUs
+ *
+ * Chapter 3: Embedded Flash Memory
+ */
+
+union __flash_acr {
+	u32_t val;
+	struct {
+		u32_t latency :4 __packed;
+		u32_t rsvd__4_7 :4 __packed;
+		u32_t prften :1 __packed;
+		u32_t arten :1 __packed;
+		u32_t rsvd__10 :1 __packed;
+		u32_t artrst :1 __packed;
+		u32_t rsvd__12_31 :20 __packed;
+	} bit;
+};
+
+/* 3.7 FLASH registers */
+struct stm32f7x_flash {
+	volatile union __flash_acr acr;
+	volatile u32_t keyr;
+	volatile u32_t optkeyr;
+	volatile u32_t sr;
+	volatile u32_t cr;
+	volatile u32_t optcr;
+	volatile u32_t optcr1;
+};
+
+#endif	/* _STM32F7X_FLASHREGISTERS_H_ */

soc/arm/st_stm32/stm32f7/gpio_registers.h

@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2018 Yurii Hamann
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _STM32F7X_GPIO_REGISTERS_H_
+#define _STM32F7X_GPIO_REGISTERS_H_
+
+/**
+ * @brief Driver for GPIO of STM32F7X family processor.
+ *
+ * Based on reference manual:
+ *   RM0385 Reference manual STM32F75xxx and STM32F74xxx
+ *   advanced ARM(r)-based 32-bit MCUs
+ *
+ * Chapter 6: General-purpose I/Os (GPIOs)
+ */
+
+/* 6.4 GPIO registers - each GPIO port controls 16 pins */
+struct stm32f7x_gpio {
+	u32_t moder;
+	u32_t otyper;
+	u32_t ospeedr;
+	u32_t pupdr;
+	u32_t idr;
+	u32_t odr;
+	u32_t bsrr;
+	u32_t lckr;
+	u32_t afr[2];
+	u32_t brr;
+};
+
+union syscfg_exticr {
+	u32_t val;
+	struct {
+		u16_t rsvd__16_31;
+		u16_t exti;
+	} bit;
+};
+
+/* 7.2 SYSCFG registers */
+struct stm32f7x_syscfg {
+	u32_t memrmp;
+	u32_t pmc;
+	union syscfg_exticr exticr1;
+	union syscfg_exticr exticr2;
+	union syscfg_exticr exticr3;
+	union syscfg_exticr exticr4;
+	u32_t cmpcr;
+};
+
+#endif /* _STM32F7X_GPIO_REGISTERS_H_ */