arm: soc: move arm SoCs to top-dir
Move the SoC outside of the architecture tree and put them at the same level as boards and architectures allowing both SoCs and boards to be maintained outside the tree. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif
parent
5744437d25
commit
70d819b405
426 changed files with 62 additions and 63 deletions
242
soc/arm/nxp_imx/mcimx7_m4/soc.c
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242
soc/arm/nxp_imx/mcimx7_m4/soc.c
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/*
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* Copyright (c) 2017, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <init.h>
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#include <soc.h>
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#include <dt-bindings/rdc/imx_rdc.h>
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#include "wdog_imx.h"
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/* Initialize clock. */
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void SOC_ClockInit(void)
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{
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/* OSC/PLL is already initialized by Cortex-A7 (u-boot) */
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/*
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* Disable WDOG3
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* Note : The WDOG clock Root is shared by all the 4 WDOGs,
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* so Zephyr code should avoid closing it
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*/
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CCM_UpdateRoot(CCM, ccmRootWdog, ccmRootmuxWdogOsc24m, 0, 0);
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CCM_EnableRoot(CCM, ccmRootWdog);
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CCM_ControlGate(CCM, ccmCcgrGateWdog3, ccmClockNeededRun);
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RDC_SetPdapAccess(RDC, rdcPdapWdog3,
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RDC_DOMAIN_PERM(M4_DOMAIN_ID, RDC_DOMAIN_PERM_RW),
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false, false);
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WDOG_DisablePowerdown(WDOG3);
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CCM_ControlGate(CCM, ccmCcgrGateWdog3, ccmClockNotNeeded);
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/* We need system PLL Div2 to run M4 core */
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CCM_ControlGate(CCM, ccmPllGateSys, ccmClockNeededRun);
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CCM_ControlGate(CCM, ccmPllGateSysDiv2, ccmClockNeededRun);
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/* Enable clock gate for IP bridge and IO mux */
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CCM_ControlGate(CCM, ccmCcgrGateIpmux1, ccmClockNeededRun);
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CCM_ControlGate(CCM, ccmCcgrGateIpmux2, ccmClockNeededRun);
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CCM_ControlGate(CCM, ccmCcgrGateIpmux3, ccmClockNeededRun);
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CCM_ControlGate(CCM, ccmCcgrGateIomux, ccmClockNeededRun);
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CCM_ControlGate(CCM, ccmCcgrGateIomuxLpsr, ccmClockNeededRun);
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/* Enable clock gate for RDC */
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CCM_ControlGate(CCM, ccmCcgrGateRdc, ccmClockNeededRun);
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}
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void SOC_RdcInit(void)
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{
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/* Move M4 core to specific RDC domain */
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RDC_SetDomainID(RDC, rdcMdaM4, M4_DOMAIN_ID, false);
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}
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#ifdef CONFIG_GPIO_IMX
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static void nxp_mcimx7_gpio_config(void)
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{
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#ifdef CONFIG_GPIO_IMX_PORT_1
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RDC_SetPdapAccess(RDC, rdcPdapGpio1, GPIO_1_RDC, false, false);
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/* Enable gpio clock gate */
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CCM_ControlGate(CCM, ccmCcgrGateGpio1, ccmClockNeededRunWait);
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#endif /* CONFIG_GPIO_IMX_PORT_1 */
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#ifdef CONFIG_GPIO_IMX_PORT_2
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RDC_SetPdapAccess(RDC, rdcPdapGpio2, GPIO_2_RDC, false, false);
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/* Enable gpio clock gate */
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CCM_ControlGate(CCM, ccmCcgrGateGpio2, ccmClockNeededRunWait);
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#endif /* CONFIG_GPIO_IMX_PORT_2 */
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#ifdef CONFIG_GPIO_IMX_PORT_7
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RDC_SetPdapAccess(RDC, rdcPdapGpio7, GPIO_7_RDC, false, false);
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/* Enable gpio clock gate */
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CCM_ControlGate(CCM, ccmCcgrGateGpio7, ccmClockNeededRunWait);
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#endif /* CONFIG_GPIO_IMX_PORT_2 */
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}
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#endif /* CONFIG_GPIO_IMX */
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#ifdef CONFIG_UART_IMX
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static void nxp_mcimx7_uart_config(void)
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{
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#ifdef CONFIG_UART_IMX_UART_2
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/* We need to grasp board uart exclusively */
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RDC_SetPdapAccess(RDC, rdcPdapUart2, UART_2_RDC, false, false);
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/* Select clock derived from OSC clock(24M) */
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CCM_UpdateRoot(CCM, ccmRootUart2, ccmRootmuxUartOsc24m, 0, 0);
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/* Enable uart clock */
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CCM_EnableRoot(CCM, ccmRootUart2);
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/*
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* IC Limitation
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* M4 stop will cause A7 UART lose functionality
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* So we need UART clock all the time
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*/
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CCM_ControlGate(CCM, ccmCcgrGateUart2, ccmClockNeededAll);
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#endif /* #ifdef CONFIG_UART_IMX_UART_2 */
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#ifdef CONFIG_UART_IMX_UART_6
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/* We need to grasp board uart exclusively */
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RDC_SetPdapAccess(RDC, rdcPdapUart6, UART_6_RDC, false, false);
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/* Select clock derived from OSC clock(24M) */
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CCM_UpdateRoot(CCM, ccmRootUart6, ccmRootmuxUartOsc24m, 0, 0);
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/* Enable uart clock */
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CCM_EnableRoot(CCM, ccmRootUart6);
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/*
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* IC Limitation
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* M4 stop will cause A7 UART lose functionality
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* So we need UART clock all the time
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*/
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CCM_ControlGate(CCM, ccmCcgrGateUart6, ccmClockNeededAll);
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#endif /* #ifdef CONFIG_UART_IMX_UART_6 */
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}
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#endif /* CONFIG_UART_IMX */
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#ifdef CONFIG_I2C_IMX
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static void nxp_mcimx7_i2c_config(void)
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{
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#ifdef CONFIG_I2C_1
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/* In this example, we need to grasp board I2C exclusively */
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RDC_SetPdapAccess(RDC, rdcPdapI2c1, I2C_1_RDC, false, false);
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/* Select I2C clock derived from OSC clock(24M) */
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CCM_UpdateRoot(CCM, ccmRootI2c1, ccmRootmuxI2cOsc24m, 0, 0);
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/* Enable I2C clock */
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CCM_EnableRoot(CCM, ccmRootI2c1);
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CCM_ControlGate(CCM, ccmCcgrGateI2c1, ccmClockNeededRunWait);
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#endif /* CONFIG_I2C_1 */
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#ifdef CONFIG_I2C_2
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/* In this example, we need to grasp board I2C exclusively */
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RDC_SetPdapAccess(RDC, rdcPdapI2c2, I2C_2_RDC, false, false);
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/* Select I2C clock derived from OSC clock(24M) */
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CCM_UpdateRoot(CCM, ccmRootI2c2, ccmRootmuxI2cOsc24m, 0, 0);
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/* Enable I2C clock */
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CCM_EnableRoot(CCM, ccmRootI2c2);
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CCM_ControlGate(CCM, ccmCcgrGateI2c2, ccmClockNeededRunWait);
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#endif /* CONFIG_I2C_2 */
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#ifdef CONFIG_I2C_3
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/* In this example, we need to grasp board I2C exclusively */
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RDC_SetPdapAccess(RDC, rdcPdapI2c3, I2C_3_RDC, false, false);
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/* Select I2C clock derived from OSC clock(24M) */
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CCM_UpdateRoot(CCM, ccmRootI2c3, ccmRootmuxI2cOsc24m, 0, 0);
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/* Enable I2C clock */
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CCM_EnableRoot(CCM, ccmRootI2c3);
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CCM_ControlGate(CCM, ccmCcgrGateI2c3, ccmClockNeededRunWait);
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#endif /* CONFIG_I2C_3 */
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#ifdef CONFIG_I2C_4
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/* In this example, we need to grasp board I2C exclusively */
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RDC_SetPdapAccess(RDC, rdcPdapI2c4, I2C_4_RDC, false, false);
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/* Select I2C clock derived from OSC clock(24M) */
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CCM_UpdateRoot(CCM, ccmRootI2c4, ccmRootmuxI2cOsc24m, 0, 0);
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/* Enable I2C clock */
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CCM_EnableRoot(CCM, ccmRootI2c4);
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CCM_ControlGate(CCM, ccmCcgrGateI2c4, ccmClockNeededRunWait);
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#endif /* CONFIG_I2C_4 */
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}
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#endif /* CONFIG_I2C_IMX */
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#ifdef CONFIG_PWM_IMX
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static void nxp_mcimx7_pwm_config(void)
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{
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#ifdef CONFIG_PWM_1
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/* We need to grasp board pwm exclusively */
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RDC_SetPdapAccess(RDC, rdcPdapPwm1, PWM_1_RDC, false, false);
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/* Select clock derived from OSC clock(24M) */
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CCM_UpdateRoot(CCM, ccmRootPwm1, ccmRootmuxPwmOsc24m, 0, 0);
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/* Enable pwm clock */
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CCM_EnableRoot(CCM, ccmRootPwm1);
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CCM_ControlGate(CCM, ccmCcgrGatePwm1, ccmClockNeededAll);
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#endif /* #ifdef CONFIG_PWM_1 */
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#ifdef CONFIG_PWM_2
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/* We need to grasp board pwm exclusively */
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RDC_SetPdapAccess(RDC, rdcPdapPwm2, PWM_2_RDC, false, false);
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/* Select clock derived from OSC clock(24M) */
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CCM_UpdateRoot(CCM, ccmRootPwm2, ccmRootmuxPwmOsc24m, 0, 0);
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/* Enable pwm clock */
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CCM_EnableRoot(CCM, ccmRootPwm2);
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CCM_ControlGate(CCM, ccmCcgrGatePwm2, ccmClockNeededAll);
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#endif /* #ifdef CONFIG_PWM_2 */
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#ifdef CONFIG_PWM_3
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/* We need to grasp board pwm exclusively */
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RDC_SetPdapAccess(RDC, rdcPdapPwm3, PWM_3_RDC, false, false);
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/* Select clock derived from OSC clock(24M) */
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CCM_UpdateRoot(CCM, ccmRootPwm3, ccmRootmuxPwmOsc24m, 0, 0);
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/* Enable pwm clock */
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CCM_EnableRoot(CCM, ccmRootPwm3);
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CCM_ControlGate(CCM, ccmCcgrGatePwm3, ccmClockNeededAll);
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#endif /* #ifdef CONFIG_PWM_3 */
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#ifdef CONFIG_PWM_4
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/* We need to grasp board pwm exclusively */
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RDC_SetPdapAccess(RDC, rdcPdapPwm4, PWM_4_RDC, false, false);
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/* Select clock derived from OSC clock(24M) */
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CCM_UpdateRoot(CCM, ccmRootPwm4, ccmRootmuxPwmOsc24m, 0, 0);
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/* Enable pwm clock */
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CCM_EnableRoot(CCM, ccmRootPwm4);
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CCM_ControlGate(CCM, ccmCcgrGatePwm4, ccmClockNeededAll);
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#endif /* #ifdef CONFIG_PWM_4 */
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}
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#endif /* CONFIG_PWM_IMX */
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static int nxp_mcimx7_init(struct device *arg)
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{
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ARG_UNUSED(arg);
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/* SoC specific RDC settings */
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SOC_RdcInit();
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/* BoC specific clock settings */
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SOC_ClockInit();
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#ifdef CONFIG_GPIO_IMX
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nxp_mcimx7_gpio_config();
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#endif /* CONFIG_GPIO_IMX */
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#ifdef CONFIG_UART_IMX
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nxp_mcimx7_uart_config();
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#endif /* CONFIG_UART_IMX */
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#ifdef CONFIG_I2C_IMX
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nxp_mcimx7_i2c_config();
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#endif /* CONFIG_I2C_IMX */
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#ifdef CONFIG_PWM_IMX
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nxp_mcimx7_pwm_config();
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#endif /* CONFIG_PWM_IMX */
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return 0;
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}
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SYS_INIT(nxp_mcimx7_init, PRE_KERNEL_1, 0);
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