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tests: drivers: stm32 clock control testing on stm32l4 / l5 mcus

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target is stm32l4x/l5x with clearing clock config
target is stm32l4x/l5x with pll 64MHz from hsi clock config
target is stm32l4x/l5x with pll 48MHz from msi clock config
target is stm32l4x/l5x with pll 64MHz from hse clock config (with bypass)
target is stm32l4x/l5x with hse, hsi, msi clock config (no pll)

Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is contained in:
Francois Ramu 2022-03-03 13:08:56 +01:00 • committed by Maureen Helm
commit 70d2b136ec
5 changed files with 69 additions and 4 deletions
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15
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/clear_clocks_msi.overlay Normal file
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@ -0,0 +1,15 @@
/*
* Copyright (c) 2022 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay clears the msi clock back to a state equivalent to what could
* be found in stm32xx.dtsi
*/
&clk_msi {
status = "disabled";
/delete-property/ msi-range;
};

30
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/pll_48_msi_4.overlay Normal file
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@ -0,0 +1,30 @@
/*
* Copyright (c) 2022 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after wb_clear_clocks.overlay file.
* It applies to the stm32xx where the msi is 4MHz
*/
&clk_msi {
status = "okay";
msi-range = <6>; /* default value */
};
&pll {
div-m = <1>;
mul-n = <24>;
div-q = <2>;
div-r = <2>;
clocks = <&clk_msi>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(48)>;
};

1
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/pll_64_hse_8.overlay
View file

@ -18,7 +18,6 @@
&pll {
div-m = <1>;
mul-n = <16>;
div-p = <2>;
div-q = <2>;
div-r = <2>;
clocks = <&clk_hse>;

1
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/boards/pll_64_hsi_16.overlay
View file

@ -16,7 +16,6 @@
&pll {
div-m = <1>;
mul-n = <8>;
div-p = <2>;
div-q = <2>;
div-r = <2>;
clocks = <&clk_hsi>;

26
tests/drivers/clock_control/stm32_clock_configuration/stm32_common/testcase.yaml
View file

@ -6,18 +6,34 @@ tests:
platform_allow: nucleo_g071rb
harness_config:
fixture: mco_sb_closed
drivers.stm32_clock_configuration.common.sysclksrc_msi_pll_64_hse_8:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/clear_clocks_msi.overlay;boards/pll_64_hse_8.overlay"
platform_allow: nucleo_l496zg nucleo_l476rg nucleo_l452re nucleo_l432kc nucleo_l4r5zi nucleo_l552ze_q
harness_config:
fixture: mco_sb_closed
drivers.stm32_clock_configuration.common.sysclksrc_pll_64_hsi_16:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_64_hsi_16.overlay"
platform_allow: nucleo_g071rb nucleo_g474re
drivers.stm32_clock_configuration.common.sysclksrc_msi_pll_64_hsi_16:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;;boards/clear_clocks_msi.overlay;boards/pll_64_hsi_16.overlay"
platform_allow: nucleo_l496zg nucleo_l476rg nucleo_l452re nucleo_l432kc nucleo_l4r5zi nucleo_l552ze_q
drivers.stm32_clock_configuration.common.sysclksrc_hsi_16:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hsi_16.overlay"
platform_allow: nucleo_g071rb nucleo_l152re nucleo_l073rz nucleo_wl55jc
drivers.stm32_clock_configuration.common.sysclksrc_msi_hsi_16:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/clear_clocks_msi.overlay;boards/hsi_16.overlay"
platform_allow: nucleo_l496zg nucleo_l476rg nucleo_l452re nucleo_l432kc nucleo_l4r5zi nucleo_l552ze_q
drivers.stm32_clock_configuration.common.sysclksrc_hse_24:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hse_24.overlay"
platform_allow: nucleo_g474re
drivers.stm32_clock_configuration.common.sysclksrc_hse_8:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hse_8.overlay"
platform_allow: nucleo_l152re nucleo_l073rz
drivers.stm32_clock_configuration.common.sysclksrc_msi_hse_8:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/clear_clocks_msi.overlay;boards/hse_8.overlay"
platform_allow: nucleo_l496zg nucleo_l476rg nucleo_l452re nucleo_l432kc nucleo_l4r5zi nucleo_l552ze_q
harness_config:
fixture: mco_sb_closed
drivers.stm32_clock_configuration.common.sysclksrc_pll_170_hse_24:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hsi_16.overlay"
platform_allow: nucleo_g474re
@ -36,12 +52,15 @@ tests:
drivers.stm32_clock_configuration.common.sysclksrc_pll_48_hse_32:
extra_args: DTC_OVERLAY_FILE="boards/wl_clear_clocks.overlay;boards/wl_pll_48_hse_32.overlay"
platform_allow: nucleo_wl55jc
drivers.stm32_clock_configuration.common.sysclksrc_32_hse:
drivers.stm32_clock_configuration.common.sysclksrc_wl_32_hse:
extra_args: DTC_OVERLAY_FILE="boards/wl_clear_clocks.overlay;boards/wl_32_hse.overlay"
platform_allow: nucleo_wl55jc
drivers.stm32_clock_configuration.common.sysclksrc_48_msi:
drivers.stm32_clock_configuration.common.sysclksrc_wl_48_msi:
extra_args: DTC_OVERLAY_FILE="boards/wl_clear_clocks.overlay;boards/msi_range11.overlay"
platform_allow: nucleo_wl55jc
drivers.stm32_clock_configuration.common.sysclksrc_48_msi:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/clear_clocks_msi.overlay;boards/msi_range11.overlay"
platform_allow: nucleo_l496zg nucleo_l476rg nucleo_l452re nucleo_l432kc nucleo_l4r5zi nucleo_l552ze_q
drivers.stm32_clock_configuration.common.sysclksrc_wb_48_msi:
extra_args: DTC_OVERLAY_FILE="boards/wb_clear_clocks.overlay;boards/msi_range11.overlay"
platform_allow: nucleo_wb55rg
@ -60,3 +79,6 @@ tests:
drivers.stm32_clock_configuration.common.sysclksrc_wb_pll_48_msi_4:
extra_args: DTC_OVERLAY_FILE="boards/wb_clear_clocks.overlay;boards/wb_pll_48_msi_4.overlay"
platform_allow: nucleo_wb55rg
drivers.stm32_clock_configuration.common.sysclksrc_msi_pll_48_msi_4:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/clear_clocks_msi.overlay;boards/pll_48_msi_4.overlay"
platform_allow: nucleo_l496zg nucleo_l476rg nucleo_l452re nucleo_l432kc nucleo_l4r5zi nucleo_l552ze_q