tests: drivers: stm32 clock control testing on stm32l4 / l5 mcus
target is stm32l4x/l5x with clearing clock config target is stm32l4x/l5x with pll 64MHz from hsi clock config target is stm32l4x/l5x with pll 48MHz from msi clock config target is stm32l4x/l5x with pll 64MHz from hse clock config (with bypass) target is stm32l4x/l5x with hse, hsi, msi clock config (no pll) Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is contained in:
parent
68add9e7e1
commit
70d2b136ec
5 changed files with 69 additions and 4 deletions
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/*
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* Copyright (c) 2022 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* Warning: This overlay clears the msi clock back to a state equivalent to what could
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* be found in stm32xx.dtsi
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*/
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&clk_msi {
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status = "disabled";
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/delete-property/ msi-range;
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};
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/*
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* Copyright (c) 2022 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* Warning: This overlay performs configuration from clean sheet.
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* It is assumed that it is applied after wb_clear_clocks.overlay file.
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* It applies to the stm32xx where the msi is 4MHz
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*/
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&clk_msi {
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status = "okay";
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msi-range = <6>; /* default value */
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};
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&pll {
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div-m = <1>;
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mul-n = <24>;
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div-q = <2>;
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div-r = <2>;
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clocks = <&clk_msi>;
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status = "okay";
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};
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&rcc {
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clocks = <&pll>;
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clock-frequency = <DT_FREQ_M(48)>;
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};
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@ -18,7 +18,6 @@
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&pll {
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&pll {
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div-m = <1>;
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div-m = <1>;
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mul-n = <16>;
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mul-n = <16>;
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div-p = <2>;
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div-q = <2>;
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div-q = <2>;
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div-r = <2>;
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div-r = <2>;
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clocks = <&clk_hse>;
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clocks = <&clk_hse>;
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@ -16,7 +16,6 @@
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&pll {
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&pll {
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div-m = <1>;
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div-m = <1>;
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mul-n = <8>;
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mul-n = <8>;
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div-p = <2>;
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div-q = <2>;
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div-q = <2>;
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div-r = <2>;
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div-r = <2>;
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clocks = <&clk_hsi>;
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clocks = <&clk_hsi>;
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@ -6,18 +6,34 @@ tests:
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platform_allow: nucleo_g071rb
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platform_allow: nucleo_g071rb
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harness_config:
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harness_config:
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fixture: mco_sb_closed
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fixture: mco_sb_closed
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drivers.stm32_clock_configuration.common.sysclksrc_msi_pll_64_hse_8:
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extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/clear_clocks_msi.overlay;boards/pll_64_hse_8.overlay"
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platform_allow: nucleo_l496zg nucleo_l476rg nucleo_l452re nucleo_l432kc nucleo_l4r5zi nucleo_l552ze_q
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harness_config:
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fixture: mco_sb_closed
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drivers.stm32_clock_configuration.common.sysclksrc_pll_64_hsi_16:
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drivers.stm32_clock_configuration.common.sysclksrc_pll_64_hsi_16:
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extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_64_hsi_16.overlay"
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extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_64_hsi_16.overlay"
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platform_allow: nucleo_g071rb nucleo_g474re
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platform_allow: nucleo_g071rb nucleo_g474re
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drivers.stm32_clock_configuration.common.sysclksrc_msi_pll_64_hsi_16:
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extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;;boards/clear_clocks_msi.overlay;boards/pll_64_hsi_16.overlay"
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platform_allow: nucleo_l496zg nucleo_l476rg nucleo_l452re nucleo_l432kc nucleo_l4r5zi nucleo_l552ze_q
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drivers.stm32_clock_configuration.common.sysclksrc_hsi_16:
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drivers.stm32_clock_configuration.common.sysclksrc_hsi_16:
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extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hsi_16.overlay"
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extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hsi_16.overlay"
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platform_allow: nucleo_g071rb nucleo_l152re nucleo_l073rz nucleo_wl55jc
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platform_allow: nucleo_g071rb nucleo_l152re nucleo_l073rz nucleo_wl55jc
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drivers.stm32_clock_configuration.common.sysclksrc_msi_hsi_16:
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extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/clear_clocks_msi.overlay;boards/hsi_16.overlay"
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platform_allow: nucleo_l496zg nucleo_l476rg nucleo_l452re nucleo_l432kc nucleo_l4r5zi nucleo_l552ze_q
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drivers.stm32_clock_configuration.common.sysclksrc_hse_24:
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drivers.stm32_clock_configuration.common.sysclksrc_hse_24:
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extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hse_24.overlay"
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extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hse_24.overlay"
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platform_allow: nucleo_g474re
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platform_allow: nucleo_g474re
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drivers.stm32_clock_configuration.common.sysclksrc_hse_8:
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drivers.stm32_clock_configuration.common.sysclksrc_hse_8:
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extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hse_8.overlay"
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extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hse_8.overlay"
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platform_allow: nucleo_l152re nucleo_l073rz
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platform_allow: nucleo_l152re nucleo_l073rz
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drivers.stm32_clock_configuration.common.sysclksrc_msi_hse_8:
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extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/clear_clocks_msi.overlay;boards/hse_8.overlay"
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platform_allow: nucleo_l496zg nucleo_l476rg nucleo_l452re nucleo_l432kc nucleo_l4r5zi nucleo_l552ze_q
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harness_config:
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fixture: mco_sb_closed
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drivers.stm32_clock_configuration.common.sysclksrc_pll_170_hse_24:
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drivers.stm32_clock_configuration.common.sysclksrc_pll_170_hse_24:
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extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hsi_16.overlay"
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extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hsi_16.overlay"
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platform_allow: nucleo_g474re
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platform_allow: nucleo_g474re
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@ -36,12 +52,15 @@ tests:
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drivers.stm32_clock_configuration.common.sysclksrc_pll_48_hse_32:
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drivers.stm32_clock_configuration.common.sysclksrc_pll_48_hse_32:
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extra_args: DTC_OVERLAY_FILE="boards/wl_clear_clocks.overlay;boards/wl_pll_48_hse_32.overlay"
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extra_args: DTC_OVERLAY_FILE="boards/wl_clear_clocks.overlay;boards/wl_pll_48_hse_32.overlay"
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platform_allow: nucleo_wl55jc
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platform_allow: nucleo_wl55jc
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drivers.stm32_clock_configuration.common.sysclksrc_32_hse:
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drivers.stm32_clock_configuration.common.sysclksrc_wl_32_hse:
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extra_args: DTC_OVERLAY_FILE="boards/wl_clear_clocks.overlay;boards/wl_32_hse.overlay"
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extra_args: DTC_OVERLAY_FILE="boards/wl_clear_clocks.overlay;boards/wl_32_hse.overlay"
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platform_allow: nucleo_wl55jc
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platform_allow: nucleo_wl55jc
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drivers.stm32_clock_configuration.common.sysclksrc_48_msi:
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drivers.stm32_clock_configuration.common.sysclksrc_wl_48_msi:
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extra_args: DTC_OVERLAY_FILE="boards/wl_clear_clocks.overlay;boards/msi_range11.overlay"
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extra_args: DTC_OVERLAY_FILE="boards/wl_clear_clocks.overlay;boards/msi_range11.overlay"
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platform_allow: nucleo_wl55jc
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platform_allow: nucleo_wl55jc
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drivers.stm32_clock_configuration.common.sysclksrc_48_msi:
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extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/clear_clocks_msi.overlay;boards/msi_range11.overlay"
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platform_allow: nucleo_l496zg nucleo_l476rg nucleo_l452re nucleo_l432kc nucleo_l4r5zi nucleo_l552ze_q
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drivers.stm32_clock_configuration.common.sysclksrc_wb_48_msi:
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drivers.stm32_clock_configuration.common.sysclksrc_wb_48_msi:
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extra_args: DTC_OVERLAY_FILE="boards/wb_clear_clocks.overlay;boards/msi_range11.overlay"
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extra_args: DTC_OVERLAY_FILE="boards/wb_clear_clocks.overlay;boards/msi_range11.overlay"
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platform_allow: nucleo_wb55rg
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platform_allow: nucleo_wb55rg
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drivers.stm32_clock_configuration.common.sysclksrc_wb_pll_48_msi_4:
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drivers.stm32_clock_configuration.common.sysclksrc_wb_pll_48_msi_4:
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extra_args: DTC_OVERLAY_FILE="boards/wb_clear_clocks.overlay;boards/wb_pll_48_msi_4.overlay"
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extra_args: DTC_OVERLAY_FILE="boards/wb_clear_clocks.overlay;boards/wb_pll_48_msi_4.overlay"
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platform_allow: nucleo_wb55rg
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platform_allow: nucleo_wb55rg
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drivers.stm32_clock_configuration.common.sysclksrc_msi_pll_48_msi_4:
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extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/clear_clocks_msi.overlay;boards/pll_48_msi_4.overlay"
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platform_allow: nucleo_l496zg nucleo_l476rg nucleo_l452re nucleo_l432kc nucleo_l4r5zi nucleo_l552ze_q
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