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drivers/clock: it51xxx: Disable eSPI pad before changing PLL sequence

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We have to disable eSPI pad before changing PLL sequence or sequence
will fail if CS# pin is low.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This commit is contained in:
Tim Lin 2025-05-21 15:28:39 +08:00 • committed by Benjamin Cabé
commit 706b7e9002
1 changed files with 12 additions and 1 deletions
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13
drivers/clock_control/clock_control_it51xxx.c
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@ -15,6 +15,7 @@
#include <zephyr/logging/log.h> #include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(clock_control_it51xxx, LOG_LEVEL_ERR); LOG_MODULE_REGISTER(clock_control_it51xxx, LOG_LEVEL_ERR);
#include "soc_espi.h"
BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1, BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
"only one ite,it51xxx-ecpm compatible node can be supported"); "only one ite,it51xxx-ecpm compatible node can be supported");
@ -171,11 +172,21 @@ static int clock_control_it51xxx_init(const struct device *dev)
ite_intc_save_and_disable_interrupts(); ite_intc_save_and_disable_interrupts();
} }
#ifdef CONFIG_ESPI
/*
* We have to disable eSPI pad before changing PLL sequence
* or sequence will fail if CS# pin is low.
*/
espi_ite_ec_enable_pad_ctrl(ESPI_ITE_SOC_DEV, false);
#endif
if (reg_val != data->pll_configuration[config->pll_freq]) { if (reg_val != data->pll_configuration[config->pll_freq]) {
/* configure PLL clock */ /* configure PLL clock */
chip_configure_pll(dev, data->pll_configuration[config->pll_freq]); chip_configure_pll(dev, data->pll_configuration[config->pll_freq]);
} }
#ifdef CONFIG_ESPI
/* Enable eSPI pad after changing PLL sequence */
espi_ite_ec_enable_pad_ctrl(ESPI_ITE_SOC_DEV, true);
#endif
if (IS_ENABLED(CONFIG_ITE_IT51XXX_INTC)) { if (IS_ENABLED(CONFIG_ITE_IT51XXX_INTC)) {
ite_intc_restore_interrupts(); ite_intc_restore_interrupts();
} }