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dts: arm: stm32f412 device has a clock 48MHz multiplexer

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Add a clk48Mhz node to the stm32f412 serie.
This clock is sourced by PLL_Q (default) or PLLI2S_Q
That 48MHz clock is used by the USB /SDMMC/RNG peripherals.
The sdmmc/SDIO clock is sourced by this CK48 (default)
or by the SYSCLOCK.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is contained in:
Francois Ramu 2024-11-26 16:35:05 +01:00 • committed by Benjamin Cabé
commit 7044876b0b
1 changed files with 8 additions and 1 deletions
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9
dts/arm/st/f4/stm32f412.dtsi
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@ -16,6 +16,13 @@
compatible = "st,stm32f411-plli2s-clock"; compatible = "st,stm32f411-plli2s-clock";
status = "disabled"; status = "disabled";
}; };
clk48: clk48 {
#clock-cells = <0>;
compatible = "st,stm32-clock-mux";
clocks = <&rcc STM32_SRC_PLL_Q CK48M_SEL(0)>;
status = "disabled";
};
}; };
soc { soc {
@ -202,7 +209,7 @@
sdmmc1: sdmmc@40012c00 { sdmmc1: sdmmc@40012c00 {
clocks = <&rcc STM32_CLOCK(APB2, 11U)>, clocks = <&rcc STM32_CLOCK(APB2, 11U)>,
<&rcc STM32_SRC_SYSCLK SDIO_SEL(1)>; <&rcc STM32_SRC_CK48 SDIO_SEL(0)>;
}; };
quadspi: quadspi@a0001000 { quadspi: quadspi@a0001000 {