diff --git a/boards/arm/mimxrt1050_evk/pinmux.c b/boards/arm/mimxrt1050_evk/pinmux.c
index eac54b48d13..44d2bb44d27 100644
--- a/boards/arm/mimxrt1050_evk/pinmux.c
+++ b/boards/arm/mimxrt1050_evk/pinmux.c
@@ -7,6 +7,7 @@
 #include <init.h>
 #include <fsl_iomuxc.h>
 #include <fsl_gpio.h>
+#include <soc.h>
 
 #ifdef CONFIG_ETH_MCUX_0
 static gpio_pin_config_t enet_gpio_config = {
@@ -16,6 +17,91 @@ static gpio_pin_config_t enet_gpio_config = {
 };
 #endif
 
+#ifdef CONFIG_DISK_ACCESS_USDHC1
+
+/*Drive Strength Field: R0(260 Ohm @ 3.3V, 150 Ohm@1.8V, 240 Ohm for DDR)
+ *Speed Field: medium(100MHz)
+ *Open Drain Enable Field: Open Drain Disabled
+ *Pull / Keep Enable Field: Pull/Keeper Enabled
+ *Pull / Keep Select Field: Pull
+ *Pull Up / Down Config. Field: 47K Ohm Pull Up
+ *Hyst. Enable Field: Hysteresis Enabled.
+ */
+
+static void mimxrt1050_evk_usdhc_pinmux(
+	u16_t nusdhc, bool init,
+	u32_t speed, u32_t strength)
+{
+	u32_t cmd_data = IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) |
+				IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
+				IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
+				IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
+				IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
+				IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
+				IOMUXC_SW_PAD_CTL_PAD_DSE(strength);
+	u32_t clk = IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) |
+				IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
+				IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
+				IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
+				IOMUXC_SW_PAD_CTL_PAD_DSE(strength);
+
+	if (nusdhc == 0) {
+		if (init) {
+			IOMUXC_SetPinMux(
+				IOMUXC_GPIO_AD_B0_05_GPIO1_IO05,
+				0U);
+			IOMUXC_SetPinMux(/*SD_CD*/
+				IOMUXC_GPIO_B1_12_GPIO2_IO28,
+				0U);
+			IOMUXC_SetPinMux(
+				IOMUXC_GPIO_B1_14_USDHC1_VSELECT,
+				0U);
+			IOMUXC_SetPinMux(
+				IOMUXC_GPIO_SD_B0_00_USDHC1_CMD,
+				0U);
+			IOMUXC_SetPinMux(
+				IOMUXC_GPIO_SD_B0_01_USDHC1_CLK,
+				0U);
+			IOMUXC_SetPinMux(
+				IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0,
+				0U);
+			IOMUXC_SetPinMux(
+				IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1,
+				0U);
+			IOMUXC_SetPinMux(
+				IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2,
+				0U);
+			IOMUXC_SetPinMux(
+				IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3,
+				0U);
+
+			IOMUXC_SetPinConfig(
+				IOMUXC_GPIO_AD_B0_05_GPIO1_IO05,
+				0x10B0u);
+			IOMUXC_SetPinConfig(/*SD0_CD_SW*/
+				IOMUXC_GPIO_B1_12_GPIO2_IO28,
+				0x017089u);
+			IOMUXC_SetPinConfig(/*SD0_VSELECT*/
+				IOMUXC_GPIO_B1_14_USDHC1_VSELECT,
+				0x0170A1u);
+		}
+
+		IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_00_USDHC1_CMD,
+			cmd_data);
+		IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_01_USDHC1_CLK,
+			clk);
+		IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0,
+			cmd_data);
+		IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1,
+			cmd_data);
+		IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2,
+			cmd_data);
+		IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3,
+			cmd_data);
+	}
+}
+#endif
+
 static int mimxrt1050_evk_init(struct device *dev)
 {
 	ARG_UNUSED(dev);
@@ -213,6 +299,11 @@ static int mimxrt1050_evk_init(struct device *dev)
 	GPIO_PinInit(GPIO2, 31, &config);
 #endif
 
+#ifdef CONFIG_DISK_ACCESS_USDHC1
+	mimxrt1050_evk_usdhc_pinmux(0, true, 2, 1);
+	imxrt_usdhc_pinmux_cb_register(mimxrt1050_evk_usdhc_pinmux);
+#endif
+
 	return 0;
 }
 
diff --git a/soc/arm/nxp_imx/rt/soc.c b/soc/arm/nxp_imx/rt/soc.c
index c86991f7cb7..9f95f015da2 100644
--- a/soc/arm/nxp_imx/rt/soc.c
+++ b/soc/arm/nxp_imx/rt/soc.c
@@ -192,6 +192,34 @@ static ALWAYS_INLINE void clkInit(void)
 
 }
 
+#if defined(CONFIG_DISK_ACCESS_USDHC1) ||	\
+	defined(CONFIG_DISK_ACCESS_USDHC2)
+
+/* Usdhc driver needs to re-configure pinmux
+ * Pinmux depends on board design.
+ * From the perspective of Usdhc driver,
+ * it can't access board specific function.
+ * So SoC provides this for board to register
+ * its usdhc pinmux and for usdhc to access
+ * pinmux.
+ */
+
+static usdhc_pin_cfg_cb g_usdhc_pin_cfg_cb;
+
+void imxrt_usdhc_pinmux_cb_register(usdhc_pin_cfg_cb cb)
+{
+	g_usdhc_pin_cfg_cb = cb;
+}
+
+void imxrt_usdhc_pinmux(u16_t nusdhc, bool init,
+	u32_t speed, u32_t strength)
+{
+	if (g_usdhc_pin_cfg_cb)
+		g_usdhc_pin_cfg_cb(nusdhc, init,
+			speed, strength);
+}
+#endif
+
 /**
  *
  * @brief Perform basic hardware initialization
diff --git a/soc/arm/nxp_imx/rt/soc.h b/soc/arm/nxp_imx/rt/soc.h
index 7a64b7e983b..9206c215aad 100644
--- a/soc/arm/nxp_imx/rt/soc.h
+++ b/soc/arm/nxp_imx/rt/soc.h
@@ -23,6 +23,18 @@ extern "C" {
  */
 #include <kernel_includes.h>
 
+#if defined(CONFIG_DISK_ACCESS_USDHC1) ||	\
+	defined(CONFIG_DISK_ACCESS_USDHC2)
+
+typedef void (*usdhc_pin_cfg_cb)(u16_t nusdhc, bool init,
+	u32_t speed, u32_t strength);
+
+void imxrt_usdhc_pinmux(u16_t nusdhc,
+	bool init, u32_t speed, u32_t strength);
+
+void imxrt_usdhc_pinmux_cb_register(usdhc_pin_cfg_cb cb);
+
+#endif
 
 #endif /* !_ASMLANGUAGE */