soc: nxp: imxrt: add config ADJUST_DCDC for RT10xx
There is a configuration of the DCDC in the clock_init for the RT10xx. The RT11xx has a kconfig flag ADJUST_DCDC to enable or disable DCDC adjust code. This flag is now also used for the RT10xx to be able to enable or disable the DCDC adjust code. Signed-off-by: Adrian Bieri <adrian.bieri@loepfe.com>
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3 changed files with 7 additions and 6 deletions
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@ -171,6 +171,10 @@ config PM_MCUX_DCDC
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config PM_MCUX_PMU
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config PM_MCUX_PMU
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bool "MCUX power management unit driver"
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bool "MCUX power management unit driver"
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config ADJUST_DCDC
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default y
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bool "Adjust internal DCDC output"
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config DCDC_VALUE
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config DCDC_VALUE
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hex "DCDC value for VDD_SOC"
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hex "DCDC value for VDD_SOC"
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@ -151,14 +151,15 @@ __weak void clock_init(void)
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/* Set PERIPH_CLK MUX to PERIPH_CLK2 */
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/* Set PERIPH_CLK MUX to PERIPH_CLK2 */
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CLOCK_SetMux(kCLOCK_PeriphMux, 0x1);
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CLOCK_SetMux(kCLOCK_PeriphMux, 0x1);
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/* Setting the VDD_SOC value.
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#if CONFIG_ADJUST_DCDC
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*/
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/* Setting the VDD_SOC value */
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DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(CONFIG_DCDC_VALUE);
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DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(CONFIG_DCDC_VALUE);
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/* Waiting for DCDC_STS_DC_OK bit is asserted */
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/* Waiting for DCDC_STS_DC_OK bit is asserted */
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while (DCDC_REG0_STS_DC_OK_MASK !=
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while (DCDC_REG0_STS_DC_OK_MASK !=
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(DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) {
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(DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) {
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;
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;
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}
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}
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#endif
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#ifdef CONFIG_INIT_ARM_PLL
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#ifdef CONFIG_INIT_ARM_PLL
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CLOCK_InitArmPll(&armPllConfig); /* Configure ARM PLL to 1200M */
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CLOCK_InitArmPll(&armPllConfig); /* Configure ARM PLL to 1200M */
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@ -69,8 +69,4 @@ config BYPASS_LDO_LPSR
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config ADJUST_LDO
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config ADJUST_LDO
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bool "Adjust LDO setting"
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bool "Adjust LDO setting"
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config ADJUST_DCDC
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default y
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bool "Adjust internal DCDC output"
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endif # SOC_SERIES_IMXRT11XX
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endif # SOC_SERIES_IMXRT11XX
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