diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/f4_i2s2_pll.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/f4_i2s2_pll.overlay new file mode 100644 index 00000000000..c40ff7de223 --- /dev/null +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/f4_i2s2_pll.overlay @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2023 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Clocks clean up config + * Aim is to avoid conflict with specific default board configuration + */ + +&clk_hse { + status = "disabled"; + /delete-property/ hse-bypass; + /delete-property/ clock-frequency; +}; + +&clk_hsi { + status = "disabled"; +}; + +&clk_lse { + status = "disabled"; +}; + +&clk_lsi { + status = "disabled"; +}; + +&pll { + /delete-property/ mul; + /delete-property/ div; + /delete-property/ prediv; + /delete-property/ xtpre; + /delete-property/ clocks; + status = "disabled"; +}; + +&rcc { + /delete-property/ clocks; + /delete-property/ clock-frequency; +}; + +&i2s2 { + /delete-property/ clocks; +}; + +/* Core set up + * Aim of this part is to provide a base working clock config + */ + +&clk_hse { + hse-bypass; + clock-frequency = ; /* STLink 8MHz clock */ + status = "okay"; +}; + +&pll { + div-m = <8>; + mul-n = <336>; + div-p = <4>; + div-q = <7>; + clocks = <&clk_hse>; + status = "okay"; +}; + +&plli2s { + mul-n = <384>; + div-r = <2>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + ahb-prescaler = <1>; + apb1-prescaler = <2>; + apb2-prescaler = <1>; +}; + +&i2s2 { + clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>, + <&rcc STM32_SRC_PLLI2S_R I2S_SEL(0)>; + pinctrl-0 = <&i2s2_ck_pb10 &i2s2_sd_pb15>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/src/test_stm32_clock_configuration.c b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/src/test_stm32_clock_configuration.c index 05ea184b15f..0193e590554 100644 --- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/src/test_stm32_clock_configuration.c +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/src/test_stm32_clock_configuration.c @@ -25,6 +25,7 @@ ZTEST(stm32_common_devices_clocks, test_sysclk_freq) CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, soc_sys_clk_freq); } +#if !defined(CONFIG_SOC_SERIES_STM32F4X) #if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c1), okay) #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v1) @@ -132,6 +133,7 @@ ZTEST(stm32_common_devices_clocks, test_i2c_clk_config) /* Not supported today */ } #endif +#endif #if DT_NODE_HAS_STATUS(DT_NODELABEL(lptim1), okay) diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/src/test_stm32_clock_configuration_i2s.c b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/src/test_stm32_clock_configuration_i2s.c new file mode 100644 index 00000000000..4235f04207b --- /dev/null +++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/src/test_stm32_clock_configuration_i2s.c @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2023 STMicroelectronics + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2s2), okay) + +#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2s) +#define DT_DRV_COMPAT st_stm32_i2s +#endif + +ZTEST(stm32_common_devices_clocks, test_i2s_clk_config) +{ + static const struct stm32_pclken pclken[] = STM32_DT_CLOCKS(DT_NODELABEL(i2s2)); + + uint32_t dev_dt_clk_freq, dev_actual_clk_freq; + uint32_t dev_actual_clk_src; + int r; + + /* Test clock_on(gating clock) */ + r = clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), + (clock_control_subsys_t) &pclken[0]); + zassert_true((r == 0), "Could not enable I2S gating clock"); + + zassert_true(__HAL_RCC_SPI2_IS_CLK_ENABLED(), "I2S2 gating clock should be on"); + TC_PRINT("I2S2 gating clock on\n"); + + zassert_true((DT_NUM_CLOCKS(DT_NODELABEL(i2s2)) > 1), "No domain clock defined in dts"); + + /* Test clock_on(domain_clk) */ + r = clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), + (clock_control_subsys_t) &pclken[1], + NULL); + zassert_true((r == 0), "Could not enable I2S domain clock"); + TC_PRINT("I2S2 domain clock configured\n"); + + /* Test clock source */ + dev_actual_clk_src = __HAL_RCC_GET_I2S_SOURCE(); + + if (pclken[1].bus == STM32_SRC_PLLI2S_R) { + zassert_equal(dev_actual_clk_src, RCC_I2SCLKSOURCE_PLLI2S, + "Expected I2S src: PLLI2S (0x%lx). Actual I2S src: 0x%x", + RCC_I2SCLKSOURCE_PLLI2S, dev_actual_clk_src); + } else { + zassert_true(0, "Unexpected domain clk (0x%x)", dev_actual_clk_src); + } + + /* Test get_rate(srce clk) */ + r = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), + (clock_control_subsys_t) &pclken[1], + &dev_dt_clk_freq); + zassert_true((r == 0), "Could not get I2S clk srce freq"); + + dev_actual_clk_freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S); + zassert_equal(dev_dt_clk_freq, dev_actual_clk_freq, + "Expected freq: %d Hz. Actual clk: %d Hz", + dev_dt_clk_freq, dev_actual_clk_freq); + + TC_PRINT("I2S2 clock source rate: %d Hz\n", dev_dt_clk_freq); + + /* Test clock_off(gating clk) */ + r = clock_control_off(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE), + (clock_control_subsys_t) &pclken[0]); + zassert_true((r == 0), "Could not disable I2S gating clk"); + + zassert_true(!__HAL_RCC_SPI2_IS_CLK_ENABLED(), "I2S2 gating clk should be off"); + TC_PRINT("I2S2 gating clk off\n"); +} +#endif