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soc: renesas: ra: ra8d1: Disable Dcache as default

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Enabling Dcache on RA8D1 will cause many issue with data coherence
in driver.
This commit disable Dcache for RA8D1 as temporary solution, user
can enable it but should be aware of data coherence issue

Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
This commit is contained in:
Duy Nguyen 2025-02-18 15:45:16 +07:00 • committed by Benjamin Cabé
commit 6f092bcdb4
2 changed files with 8 additions and 2 deletions
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5
soc/renesas/ra/ra8d1/Kconfig.defconfig
View file

@ -21,7 +21,10 @@ config CLOCK_CONTROL
config FLASH_FILL_BUFFER_SIZE
default 128
config DCACHE
default n
config CACHE_MANAGEMENT
default y
default n
endif # SOC_SERIES_RA8D1

5
soc/renesas/ra/ra8d1/soc.c
View file

@ -39,10 +39,12 @@ void soc_early_init_hook(void)
SystemCoreClock = BSP_MOCO_HZ;
g_protect_pfswe_counter = 0;
#ifdef CONFIG_ICACHE
SCB->CCR = (uint32_t)CCR_CACHE_ENABLE;
barrier_dsync_fence_full();
barrier_isync_fence_full();
#endif
#if defined(CONFIG_DCACHE) && defined(CONFIG_CACHE_MANAGEMENT)
/* Apply Arm Cortex-M85 errata workarounds for D-Cache
* Attributing all cacheable memory as write-through set FORCEWT bit in MSCR register.
* Set bit 16 in ACTLR to 1.
@ -58,4 +60,5 @@ void soc_early_init_hook(void)
barrier_isync_fence_full();
sys_cache_data_enable();
#endif
}