boards: st: add nucleo_u385rg_q board support

add board support for nucleo_u385rg_q

Signed-off-by: Khaoula Bidani <khaoula.bidani-ext@st.com>

boards/st/nucleo_u385rg_q/Kconfig.nucleo_u385rg_q

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+# Copyright (c) 2025 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_NUCLEO_U385RG_Q
+	select SOC_STM32U385XX

boards/st/nucleo_u385rg_q/arduino_r3_connector.dtsi

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+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	arduino_header: connector {
+		compatible = "arduino-header-r3";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map = <0 0 &gpioa 0 0>,	/* A0 */
+			   <1 0 &gpioa 1 0>,	/* A1 */
+			   <2 0 &gpioa 4 0>,	/* A2 */
+			   <3 0 &gpiob 0 0>,	/* A3 */
+			   <4 0 &gpioc 1 0>,	/* A4 */
+			   <5 0 &gpioc 0 0>,	/* A5 */
+			   <6 0 &gpioa 3 0>,	/* D0 */
+			   <7 0 &gpioa 2 0>,	/* D1 */
+			   <8 0 &gpioc 8 0>,	/* D2 */
+			   <9 0 &gpiob 3 0>,	/* D3 */
+			   <10 0 &gpiob 5 0>,	/* D4 */
+			   <11 0 &gpiob 4 0>,	/* D5 */
+			   <12 0 &gpiob 10 0>,	/* D6 */
+			   <13 0 &gpioa 8 0>,	/* D7 */
+			   <14 0 &gpioc 7 0>,	/* D8 */
+			   <15 0 &gpioc 6 0>,	/* D9 */
+			   <16 0 &gpiob 9 0>,	/* D10 */
+			   <17 0 &gpioa 7 0>,	/* D11 */
+			   <18 0 &gpioa 6 0>,	/* D12 */
+			   <19 0 &gpioa 5 0>,	/* D13 */
+			   <20 0 &gpiob 7 0>,	/* D14 */
+			   <21 0 &gpiob 6 0>;	/* D15 */
+	};
+};
+
+arduino_serial: &lpuart1 {};

boards/st/nucleo_u385rg_q/board.cmake

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+# keep first
+board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
+board_runner_args(pyocd "--target=stm32u385rgtxq")
+board_runner_args(jlink "--device=STM32U385RG" "--reset-after-load")
+
+# keep first
+include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)

boards/st/nucleo_u385rg_q/board.yml

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+board:
+  name: nucleo_u385rg_q
+  full_name: Nucleo U385RG Q
+  vendor: st
+  socs:
+    - name: stm32u385xx

boards/st/nucleo_u385rg_q/doc/index.rst

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+.. zephyr:board:: nucleo_u385rg_q
+
+Overview
+********
+
+The Nucleo U385RG board, featuring an ARM |reg| Cortex |reg| -M33 with
+TrustZone |reg| based STM32U385RG MCU, provides an affordable and flexible
+way for users to try out new concepts and build prototypes by choosing from
+the various combinations of performance and power consumption features.
+Here are some highlights of the Nucleo U385RG board:
+
+- STM32U385RG microcontroller in an LQFP64 or LQFP48 package
+- Two types of extension resources:
+
+  - Arduino |reg| Uno V3 connectivity
+  - ST morpho extension pin headers for full access to all STM32U3 I/Os
+
+- On-board STLINK-V2EC debugger/programmer with USB re-enumeration
+  capability: mass storage, Virtual COM port, and debug port
+- Flexible board power supply:
+
+  - USB VBUS or external source(3.3V, 5V, 7 - 12V)
+
+- Two push-buttons: USER and RESET
+- 32.768 kHz crystal oscillator
+- Second user LED shared with ARDUINO |reg| Uno V3
+- External or internal SMPS to generate Vcore logic supply
+- 24 MHz or 48 MHz HSE
+- User USB Device full speed, or USB SNK/UFP full speed
+- Cryptography
+- CAN FD transceiver
+- Board connectors:
+
+ - External SMPS experimentation dedicated connector
+ - USB Type-C |reg| , Micro-B, or Mini-B connector for the ST-LINK
+ - USB Type-C |reg| user connector
+ - MIPI |reg| debug connector
+ - CAN FD header
+
+More information about the board can be found at the `NUCLEO_U385RG website`_.
+
+Hardware
+********
+
+The STM32U385xx devices are an ultra-low-power microcontrollers family (STM32U3
+Series) based on the high-performance Arm |reg| Cortex |reg|-M33 32-bit RISC core.
+They operate at a frequency of up to 96 MHz.
+
+- Includes ST state-of-the-art patented technology
+- Ultra-low-power with FlexPowerControl:
+
+  - 1.71 V to 3.6 V power supply
+  - -40 °C to +105 °C temperature range
+  - VBAT mode: supply for RTC, 32 x 32-bit backup registers
+  - 1.6 μA Stop 3 mode with 8-Kbyte SRAM
+  - 2.2 μA Stop 3 mode with full SRAM
+  - 3.8 μA Stop 2 mode with 8-Kbyte SRAM
+  - 4.5 μA Stop 2 mode with full SRAM
+  - 9.5 μA/MHz Run mode @ 3.3 V (While(1) SMPS step-down converter mode)
+  - 13 μA/MHz Run mode @ 3.3 V/48 MHz (CoreMark |reg| SMPS step-down converter mode)
+  - 16 μA/MHz Run mode @ 3.3 V/96 MHz (CoreMark |reg| SMPS step-down converter mode)
+  - Brownout reset
+
+- Core:
+
+  - 32-bit Arm |reg| Cortex |reg|-M33 CPU with TrustZone |reg| and FPU
+
+- ART Accelerator:
+
+  - 8-Kbyte instruction cache allowing 0-wait-state execution from flash and external memories:
+    frequency up to 96 MHz, MPU, 144 DMIPS and DSP instructions
+
+- Power management:
+
+  - Embedded regulator (LDO) and SMPS step-down converter supporting switch on-the-fly and voltage scaling
+
+- Benchmarks:
+
+  - 1.5 DMIPS/MHz (Drystone 2.1)
+  - 387 CoreMark |reg| (4.09 CoreMark/MHz at 56 MHz)
+  - 500 ULPMark |trade| -CP
+  - 117 ULPMark |trade| -CM
+  - 202000 SecureMark |trade| -TLS
+
+- Memories:
+
+  - 1-Mbyte flash memory with ECC, 2 banks read-while-write
+  - 256 Kbytes of SRAM including 64 Kbytes with hardware parity check
+  - OCTOSPI external memory interface supporting SRAM, PSRAM, NOR, NAND, and FRAM memories
+
+- General-purpose input/outputs:
+
+  - Up to 82 fast I/Os with interrupt capability most 5 V-tolerant and up to 14 I/Os with independent supply down to 1.08 V
+
+- Clock management:
+
+  - 4 to 50 MHz crystal oscillator
+  - 32.768 kHz crystal oscillator for RTC (LSE)
+  - Internal 16 MHz factory-trimmed RC (±1 %)
+  - Internal low-power RC with frequency 32 kHz or 250 Hz (±5 %)
+  - 2 internal multispeed 3 MHz to 96 MHz oscillators
+  - Internal 48 MHz with clock recovery
+  - Accurate MSI in PLL-mode and up to 96 MHz with 32.768 kHz, 16 MHz, or 32 MHz crystal oscillator
+
+- Security and cryptography:
+
+  - Arm |reg| TrustZone |reg| and securable I/Os, memories, and peripherals
+  - Flexible life cycle scheme with RDP and password protected debug
+  - Root of trust due to unique boot entry and secure hide protection area (HDP)
+  - Secure firmware installation (SFI) from embedded root secure services (RSS)
+  - Secure data storage with hardware unique key (HUK)
+  - Secure firmware upgrade
+  - Support of Trusted firmware for Cortex |reg| M (TF-M)
+  - Two AES coprocessors, one with side channel attack resistance (SCA) (SAES)
+  - Public key accelerator, SCA resistant
+  - Key hardware protection
+  - Attestation keys
+  - HASH hardware accelerator
+  - True random number generator, NIST SP800-90B compliant
+  - 96-bit unique ID
+  - 512-byte OTP (one-time programmable)
+  - Antitamper protection
+
+- Up to 15 timers and 2 watchdogs :
+
+  - 1x 16-bit advanced motor-control
+  - 3x 32-bit and 3x 16-bit general purpose
+  - 2x 16-bit basic
+  - 4x low-power 16-bit timers (available in Stop mode)
+  - 2x watchdogs
+  - 2x SysTick timer
+  - RTC with hardware calendar
+  - Alarms
+  - Calibration
+
+- Up to 19 communication peripherals:
+
+  - 1 USB 2.0 full-speed controller
+  - 1 SAI (serial audio interface)
+  - 3 I2C FM+(1 Mbit/s), SMBus/PMBus |trade|
+  - 2 I3C (SDR), with support of I2C FM+ mode
+  - 2 USARTs and 2 UARTs (SPI, ISO 7816, LIN, IrDA, modem), 1 LPUART
+  - 3 SPIs (6 SPIs including 1 with OCTOSPI + 2 with USART)
+  - 1 CAN FD controller
+  - 1 SDMMC interface
+  - 1 audio digital filter with sound-activity detection
+
+- 12-channel GPDMA controller, functional in Sleep and Stop modes (up to Stop 2)
+- Up to 21 capacitive sensing channels:
+
+  - Support touch key, linear, and rotary touch sensors
+
+- Rich analog peripherals (independent supply):
+
+  - 2x 12-bit ADC 2.5 Msps, with hardware oversampling
+  - 12-bit DAC module with 2 D/A converters, low-power sample and hold, autonomous in Stop 1 mode
+  - 2 operational amplifiers with built-in PGA
+  - 2 ultralow-power comparators
+
+- CRC calculation unit
+- Debug:
+
+  - Development support: serial-wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| (ETM)
+
+- ECOPACK2 compliant packages
+
+More information about STM32U385RG can be found here:
+
+- `STM32U385RG on www.st.com`_
+- `STM32U385RG reference manual`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Connections and IOs
+===================
+
+Nucleo U385RG Board has 14 GPIO controllers. These controllers are responsible
+for pin muxing, input/output, pull-up, etc.
+
+For more details please refer to `STM32U385 User Manual`_.
+
+Default Zephyr Peripheral Mapping:
+----------------------------------
+
+- DAC1_OUT1 : PA4
+- LD4 : PA5
+- LPUART_1_TX : PA2
+- LPUART_1_RX : PA3
+- UART_1_TX : PA9
+- UART_1_RX : PA10
+- UART_3_TX : PC10
+- UART_3_RX : PC11
+- USER_PB : PC13
+
+System Clock
+------------
+
+Nucleo U385RG System Clock could be driven by internal or external oscillator,
+as well as main PLL clock. By default System clock is driven by PLL clock at
+48MHz, driven by 4MHz medium speed internal oscillator.
+
+Serial Port
+-----------
+
+Nucleo U385RG board has 4 U(S)ARTs, 1 LPUART. The Zephyr console output is assigned to
+USART1. Default settings are 115200 8N1.
+
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Nucleo U385RG board includes an ST-LINK/V3 embedded debug tool interface.
+This probe allows to flash the board using various tools.
+
+Flashing
+========
+
+The board is configured to be flashed using west `STM32CubeProgrammer`_ runner,
+so its :ref:`installation <stm32cubeprog-flash-host-tools>` is required.
+
+Alternatively, JLink or pyOCD can also be used to flash the board using
+the ``--runner`` (or ``-r``) option:
+
+.. code-block:: console
+
+   $ west flash --runner pyocd
+   $ west flash --runner jlink
+
+For pyOCD, additional target information needs to be installed
+by executing the following pyOCD commands:
+
+.. code-block:: console
+
+   $ pyocd pack --update
+   $ pyocd pack --install stm32u3
+
+
+Flashing an application to Nucleo U385RG
+----------------------------------------
+
+Connect the Nucleo U385RG to your host computer using the USB port.
+Then build and flash an application. Here is an example for the
+:zephyr:code-sample:`hello_world` application.
+
+Run a serial host program to connect with your Nucleo board:
+
+.. code-block:: console
+
+   $ minicom -D /dev/ttyACM0
+
+Then build and flash the application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: nucleo_u385rg_q
+   :goals: build flash
+
+You should see the following message on the console:
+
+.. code-block:: console
+
+   Hello World! nucleo_u385rg_q
+
+Debugging
+=========
+
+Default debugger for this board is OpenOCD. It can be used in the usual way.
+Here is an example for the :zephyr:code-sample:`blinky` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/basic/blinky
+   :board: nucleo_u385rg_q
+   :goals: debug
+
+Note: Check the ``build/tfm`` directory to ensure that the commands required by these scripts
+(``readlink``, etc.) are available on your system. Please also check ``STM32_Programmer_CLI``
+(which is used for initialization) is available in the PATH.
+
+.. _NUCLEO_U385RG website:
+  https://www.st.com/en/evaluation-tools/nucleo-u385rg.html
+
+.. _STM32U385 User Manual:
+   https://www.st.com/resource/en/user_manual/um3261-stm32u3-series-safety-manual-stmicroelectronics.pdf
+
+.. _STM32U385RG on www.st.com:
+   https://www.st.com/en/microcontrollers-microprocessors/stm32u385rg
+
+.. _STM32U385RG reference manual:
+   https://www.st.com/resource/en/reference_manual/rm0503-stm32u3-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf
+
+.. _STM32CubeProgrammer:
+   https://www.st.com/en/development-tools/stm32cubeprog.html

boards/st/nucleo_u385rg_q/nucleo_u385rg_q.dts

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+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <st/u3/stm32u385Xg.dtsi>
+#include <st/u3/stm32u385rgtxq-pinctrl.dtsi>
+#include "arduino_r3_connector.dtsi"
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	model = "STMicroelectronics STM32U385RG-NUCLEO-Q board";
+	compatible = "st,stm32u385rg-nucleo-q";
+
+	chosen {
+		zephyr,console = &usart1;
+		zephyr,shell-uart = &usart1;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+	};
+
+	leds: leds {
+		compatible = "gpio-leds";
+
+		green_led_2: led_2 {
+			gpios = <&gpioa 5 GPIO_ACTIVE_HIGH>;
+			label = "User LD4";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+
+		user_button: button {
+			label = "User";
+			gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
+			zephyr,code = <INPUT_KEY_0>;
+		};
+	};
+
+	aliases {
+		led0 = &green_led_2;
+		sw0 = &user_button;
+	};
+};
+
+&usart1 {
+	pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+	status = "okay";
+};
+
+&usart3 {
+	pinctrl-0 = <&usart3_tx_pc10 &usart3_rx_pc11>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+	status = "okay";
+};
+
+&lpuart1 {
+	pinctrl-0 = <&lpuart1_tx_pa2 &lpuart1_rx_pa3>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+	status = "okay";
+};
+
+&clk_hsi {
+	status = "okay";
+};
+
+&clk_lse {
+	status = "okay";
+};
+
+&clk_msis {
+	status = "okay";
+	msi-pll-mode;
+	msi-range = <0>; /* 96MHz (reset value) */
+};
+
+&rcc {
+	clocks = <&clk_msis>;
+	clock-frequency = <DT_FREQ_M(96)>;
+	ahb-prescaler = <1>;
+	apb1-prescaler = <1>;
+	apb2-prescaler = <1>;
+	apb3-prescaler = <1>;
+};
+
+&clk_lsi {
+	status = "okay";
+};

boards/st/nucleo_u385rg_q/nucleo_u385rg_q.yaml

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+identifier: nucleo_u385rg_q
+name: ST Nucleo U385RG Q
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+supported:
+  - arduino_gpio
+  - gpio
+  - usart
+ram: 256
+flash: 1024

boards/st/nucleo_u385rg_q/nucleo_u385rg_q_defconfig

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+# SPDX-License-Identifier: Apache-2.0
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable GPIO driver
+CONFIG_GPIO=y