soc: renesas: Add initial support for RA4W1 SOC

Initial commit to support Renesas RA4W1 SOC

Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>

dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi

@@ -0,0 +1,146 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/clock/ra_clock.h>
+#include <arm/renesas/ra/ra4/ra4-cm4-common.dtsi>
+
+/ {
+	soc {
+		sram0: memory@20000000 {
+			compatible = "mmio-sram";
+			reg = <0x20000000 DT_SIZE_K(96)>;
+		};
+
+		flash-controller@407e0000 {
+			flash0: flash@0 {
+				compatible = "soc-nv-flash";
+				reg = <0x0 DT_SIZE_K(512)>;
+			};
+		};
+
+		sci4: sci4@40070080  {
+			compatible = "renesas,ra-sci";
+			interrupts = <16 1>, <17 1>, <18 1>, <19 1>;
+			interrupt-names = "rxi", "txi", "tei", "eri";
+			reg = <0x40070080 0x20>;
+			clocks = <&pclka MSTPB 26>;
+			status = "disabled";
+			uart {
+				compatible = "renesas,ra-sci-uart";
+				channel = <4>;
+				status = "disabled";
+			};
+		};
+	};
+
+	clocks: clocks {
+		xtal: clock-xtal {
+			compatible = "renesas,ra-cgc-external-clock";
+			clock-frequency = <DT_FREQ_M(8)>;
+			#clock-cells = <0>;
+			status = "disabled";
+		};
+
+		hoco: clock-hoco {
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(48)>;
+			#clock-cells = <0>;
+		};
+
+		moco: clock-moco {
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(8)>;
+			#clock-cells = <0>;
+		};
+
+		loco: clock-loco {
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			#clock-cells = <0>;
+		};
+
+		subclk: clock-subclk {
+			compatible = "renesas,ra-cgc-subclk";
+			clock-frequency = <32768>;
+			#clock-cells = <0>;
+			status = "disabled";
+		};
+
+		pll: pll {
+			compatible = "renesas,ra-cgc-pll";
+			#clock-cells = <0>;
+
+			/* PLL */
+			source = <RA_PLL_SOURCE_MAIN_OSC>;
+			div = <RA_PLL_DIV_2>;
+			mul = <12 0>;
+			freq = <DT_FREQ_M(48)>;
+			status = "disabled";
+		};
+
+		pclkblock: pclkblock {
+			compatible = "renesas,ra-cgc-pclk-block";
+			#clock-cells = <0>;
+			sysclock-src = <RA_CLOCK_SOURCE_HOCO>;
+			status = "okay";
+
+			iclk: iclk {
+				compatible = "renesas,ra-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_1>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclka: pclka {
+				compatible = "renesas,ra-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_1>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclkb: pclkb {
+				compatible = "renesas,ra-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_2>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclkc: pclkc {
+				compatible = "renesas,ra-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_1>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclkd: pclkd {
+				compatible = "renesas,ra-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_1>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			fclk: fclk {
+				compatible = "renesas,ra-cgc-pclk";
+				clk_div = <RA_SYS_CLOCK_DIV_2>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			clkout: clkout {
+				compatible = "renesas,ra-cgc-pclk";
+				#clock-cells = <2>;
+				status = "disabled";
+			};
+
+			uclk: uclk {
+				compatible = "renesas,ra-cgc-pclk";
+				clk_div = <RA_USB_CLOCK_DIV_1>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+		};
+	};
+};

dts/arm/renesas/ra/ra4/ra4-cm4-common.dtsi

@@ -0,0 +1,174 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <arm/armv7-m.dtsi>
+#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h>
+#include <freq.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m4";
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			mpu: mpu@e000ed90 {
+				compatible = "arm,armv7m-mpu";
+				reg = <0xe000ed90 0x40>;
+			};
+
+		};
+	};
+
+	soc {
+		system: system@4001e000 {
+			compatible = "renesas,ra-system";
+			reg = <0x4001e000 0x1000>;
+			status = "okay";
+		};
+
+		flash-controller@407e0000 {
+			reg = <0x407e0000 0x10000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
+
+		ioport0: gpio@40040000 {
+			compatible = "renesas,ra-gpio-ioport";
+			reg = <0x40040000 0x20>;
+			port = <0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+			status = "disabled";
+		};
+
+		ioport1: gpio@40040020 {
+			compatible = "renesas,ra-gpio-ioport";
+			reg = <0x40040020 0x20>;
+			port = <1>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+			status = "disabled";
+		};
+
+		ioport2: gpio@40040040 {
+			compatible = "renesas,ra-gpio-ioport";
+			reg = <0x40040040 0x20>;
+			port = <2>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+			status = "disabled";
+		};
+
+		ioport3: gpio@40040060 {
+			compatible = "renesas,ra-gpio-ioport";
+			reg = <0x40040060 0x20>;
+			port = <3>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+			status = "disabled";
+		};
+
+		ioport4: gpio@40040080 {
+			compatible = "renesas,ra-gpio-ioport";
+			reg = <0x40040080 0x20>;
+			port = <4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+			status = "disabled";
+		};
+
+		ioport5: gpio@400400a0 {
+			compatible = "renesas,ra-gpio-ioport";
+			reg = <0x400400a0 0x20>;
+			port = <5>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+			status = "disabled";
+		};
+
+		ioport9: gpio@40040120 {
+			compatible = "renesas,ra-gpio-ioport";
+			reg = <0x40040120 0x20>;
+			port = <9>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+			status = "disabled";
+		};
+
+		pinctrl: pin-controller@40040800 {
+			compatible = "renesas,ra-pinctrl-pfs";
+			reg = <0x40040800 0x3c0>;
+			status = "okay";
+		};
+
+		sci0: sci0@40070000  {
+			compatible = "renesas,ra-sci";
+			interrupts = <0 1>, <1 1>, <2 1>, <3 1>;
+			interrupt-names = "rxi", "txi", "tei", "eri";
+			reg = <0x40070000 0x20>;
+			clocks = <&pclka MSTPB 31>;
+			status = "disabled";
+			uart {
+				compatible = "renesas,ra-sci-uart";
+				channel = <0>;
+				status = "disabled";
+			};
+		};
+
+		sci1: sci1@40070020  {
+			compatible = "renesas,ra-sci";
+			interrupts = <4 1>, <5 1>, <6 1>, <7 1>;
+			interrupt-names = "rxi", "txi", "tei", "eri";
+			reg = <0x40070020 0x20>;
+			clocks = <&pclka MSTPB 30>;
+			status = "disabled";
+			uart {
+				compatible = "renesas,ra-sci-uart";
+				channel = <1>;
+				status = "disabled";
+			};
+		};
+
+		sci9: sci9@40070120  {
+			compatible = "renesas,ra-sci";
+			interrupts = <36 1>, <37 1>, <38 1>, <39 1>;
+			interrupt-names = "rxi", "txi", "tei", "eri";
+			reg = <0x40070120 0x20>;
+			clocks = <&pclka MSTPB 22>;
+			status = "disabled";
+			uart {
+				compatible = "renesas,ra-sci-uart";
+				channel = <9>;
+				status = "disabled";
+			};
+		};
+
+		id_code: id_code@1010018 {
+			compatible = "zephyr,memory-region";
+			reg = <0x01010018 0x20>;
+			zephyr,memory-region = "ID_CODE";
+			status = "okay";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <4>;
+};

soc/renesas/ra/ra4w1/CMakeLists.txt

@@ -0,0 +1,14 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+zephyr_sources(
+  soc.c
+)
+
+zephyr_linker_sources(ROM_START opt_set_mem.ld)
+
+zephyr_linker_sources(SECTIONS sections.ld)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

soc/renesas/ra/ra4w1/Kconfig

@@ -0,0 +1,13 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RA4W1
+	select ARM
+	select CPU_HAS_ARM_MPU
+	select CPU_CORTEX_M4
+	select HAS_RENESAS_RA_FSP
+	select CPU_CORTEX_M_HAS_DWT
+	select CPU_HAS_FPU
+	select FPU
+	select HAS_SWO
+	select XIP

soc/renesas/ra/ra4w1/Kconfig.defconfig

@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_RA4W1
+
+config NUM_IRQS
+	default 32
+
+config PINCTRL
+	default y
+
+endif # SOC_SERIES_RA4W1

soc/renesas/ra/ra4w1/Kconfig.soc

@@ -0,0 +1,20 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RA4W1
+	bool
+	select SOC_FAMILY_RENESAS_RA
+	help
+	  Renesas RA4W1 series
+
+config SOC_R7FA4W1AD2CNG
+	bool
+	select SOC_SERIES_RA4W1
+	help
+	  R7FA4W1AD2CNG
+
+config SOC_SERIES
+	default "ra4w1" if SOC_SERIES_RA4W1
+
+config SOC
+	default "r7fa4w1ad2cng" if SOC_R7FA4W1AD2CNG

soc/renesas/ra/ra4w1/opt_set_mem.ld

@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* ROM Registers start at address 0x00000400 */
+. = 0x400;
+KEEP(*(.rom_registers*))
+/* Reserving 0x100 bytes of space for ROM registers. */
+. = 0x500;

soc/renesas/ra/ra4w1/sections.ld

@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+.code_in_ram :
+{
+	. = ALIGN(4);
+	__Code_In_RAM_Start = .;
+	KEEP(*(.code_in_ram*))
+	__Code_In_RAM_End = .;
+} > RAMABLE_REGION
+
+SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
+{
+	/* If DTC is used, put the DTC vector table at the start of SRAM.
+		This avoids memory holes due to 1K alignment required by it. */
+	*(.fsp_dtc_vector_table)
+} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
+
+SECTION_PROLOGUE(.id_code,,)
+{
+    KEEP(*(.id_code*))
+} GROUP_LINK_IN(ID_CODE)

soc/renesas/ra/ra4w1/soc.c

@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for Renesas RA4W1 family processor
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/arch/cpu.h>
+#include <cmsis_core.h>
+#include <zephyr/arch/arm/nmi.h>
+#include <zephyr/irq.h>
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
+
+#include "bsp_cfg.h"
+#include <bsp_api.h>
+
+uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
+
+volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ * So the init priority has to be 0 (zero).
+ *
+ * @return 0
+ */
+static int renesas_ra4w1_init(void)
+{
+	SystemCoreClock = BSP_MOCO_HZ;
+	g_protect_pfswe_counter = 0;
+	bsp_clock_init();
+
+	return 0;
+}
+
+SYS_INIT(renesas_ra4w1_init, PRE_KERNEL_1, 0);

soc/renesas/ra/ra4w1/soc.h

@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file SoC configuration macros for the Renesas RA4W1 family MCU
+ */
+
+#ifndef ZEPHYR_SOC_RENESAS_RA4W1_SOC_H_
+#define ZEPHYR_SOC_RENESAS_RA4W1_SOC_H_
+
+#include <bsp_api.h>
+
+#endif /* ZEPHYR_SOC_RENESAS_RA4W1_SOC_H_ */

soc/renesas/ra/soc.yml

@@ -16,6 +16,9 @@ family:
       - name: ra4m3
         socs:
           - name: r7fa4m3af3cfb
+      - name: ra4w1
+        socs:
+          - name: r7fa4w1ad2cng
       - name: ra6m1
         socs:
           - name: r7fa6m1ad3cfp