soc: renesas: Add initial support for RA4W1 SOC

Initial commit to support Renesas RA4W1 SOC

Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>

soc/renesas/ra/ra4w1/CMakeLists.txt

@@ -0,0 +1,14 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+zephyr_sources(
+  soc.c
+)
+
+zephyr_linker_sources(ROM_START opt_set_mem.ld)
+
+zephyr_linker_sources(SECTIONS sections.ld)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

soc/renesas/ra/ra4w1/Kconfig

@@ -0,0 +1,13 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RA4W1
+	select ARM
+	select CPU_HAS_ARM_MPU
+	select CPU_CORTEX_M4
+	select HAS_RENESAS_RA_FSP
+	select CPU_CORTEX_M_HAS_DWT
+	select CPU_HAS_FPU
+	select FPU
+	select HAS_SWO
+	select XIP

soc/renesas/ra/ra4w1/Kconfig.defconfig

@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_RA4W1
+
+config NUM_IRQS
+	default 32
+
+config PINCTRL
+	default y
+
+endif # SOC_SERIES_RA4W1

soc/renesas/ra/ra4w1/Kconfig.soc

@@ -0,0 +1,20 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RA4W1
+	bool
+	select SOC_FAMILY_RENESAS_RA
+	help
+	  Renesas RA4W1 series
+
+config SOC_R7FA4W1AD2CNG
+	bool
+	select SOC_SERIES_RA4W1
+	help
+	  R7FA4W1AD2CNG
+
+config SOC_SERIES
+	default "ra4w1" if SOC_SERIES_RA4W1
+
+config SOC
+	default "r7fa4w1ad2cng" if SOC_R7FA4W1AD2CNG

soc/renesas/ra/ra4w1/opt_set_mem.ld

@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* ROM Registers start at address 0x00000400 */
+. = 0x400;
+KEEP(*(.rom_registers*))
+/* Reserving 0x100 bytes of space for ROM registers. */
+. = 0x500;

soc/renesas/ra/ra4w1/sections.ld

@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+.code_in_ram :
+{
+	. = ALIGN(4);
+	__Code_In_RAM_Start = .;
+	KEEP(*(.code_in_ram*))
+	__Code_In_RAM_End = .;
+} > RAMABLE_REGION
+
+SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
+{
+	/* If DTC is used, put the DTC vector table at the start of SRAM.
+		This avoids memory holes due to 1K alignment required by it. */
+	*(.fsp_dtc_vector_table)
+} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
+
+SECTION_PROLOGUE(.id_code,,)
+{
+    KEEP(*(.id_code*))
+} GROUP_LINK_IN(ID_CODE)

soc/renesas/ra/ra4w1/soc.c

@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for Renesas RA4W1 family processor
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/arch/cpu.h>
+#include <cmsis_core.h>
+#include <zephyr/arch/arm/nmi.h>
+#include <zephyr/irq.h>
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
+
+#include "bsp_cfg.h"
+#include <bsp_api.h>
+
+uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
+
+volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ * So the init priority has to be 0 (zero).
+ *
+ * @return 0
+ */
+static int renesas_ra4w1_init(void)
+{
+	SystemCoreClock = BSP_MOCO_HZ;
+	g_protect_pfswe_counter = 0;
+	bsp_clock_init();
+
+	return 0;
+}
+
+SYS_INIT(renesas_ra4w1_init, PRE_KERNEL_1, 0);

soc/renesas/ra/ra4w1/soc.h

@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file SoC configuration macros for the Renesas RA4W1 family MCU
+ */
+
+#ifndef ZEPHYR_SOC_RENESAS_RA4W1_SOC_H_
+#define ZEPHYR_SOC_RENESAS_RA4W1_SOC_H_
+
+#include <bsp_api.h>
+
+#endif /* ZEPHYR_SOC_RENESAS_RA4W1_SOC_H_ */

soc/renesas/ra/soc.yml

@@ -16,6 +16,9 @@ family:
       - name: ra4m3
         socs:
           - name: r7fa4m3af3cfb
+      - name: ra4w1
+        socs:
+          - name: r7fa4w1ad2cng
       - name: ra6m1
         socs:
           - name: r7fa6m1ad3cfp