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drivers/clock_control: stm32u5: Centralize flash_latency update

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Flash latency setting could be factorized in a single location,
rather than split in each clock setting function.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2022-03-04 10:59:33 +01:00 • committed by Carles Cufí
commit 6dfe13120c
1 changed files with 30 additions and 53 deletions
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83
drivers/clock_control/clock_stm32_ll_u5.c
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@ -114,6 +114,19 @@ static uint32_t get_pllsrc_frequency(void)
return 0; return 0;
} }
static uint32_t get_startup_frequency(void)
{
switch (LL_RCC_GetSysClkSource()) {
case LL_RCC_SYS_CLKSOURCE_STATUS_MSIS:
return get_msis_frequency();
case LL_RCC_SYS_CLKSOURCE_STATUS_HSI:
return STM32_HSI_FREQ;
default:
__ASSERT(0, "Unexpected startup freq");
return 0;
}
}
static inline int stm32_clock_control_on(const struct device *dev, static inline int stm32_clock_control_on(const struct device *dev,
clock_control_subsys_t sub_system) clock_control_subsys_t sub_system)
{ {
@ -338,24 +351,6 @@ void config_src_sysclk_hse(LL_UTILS_ClkInitTypeDef s_ClkInitStruct)
{ {
#ifdef STM32_SYSCLK_SRC_HSE #ifdef STM32_SYSCLK_SRC_HSE
uint32_t old_hclk_freq;
uint32_t new_hclk_freq;
old_hclk_freq = HAL_RCC_GetHCLKFreq();
/* Calculate new SystemCoreClock variable based on HSE freq */
new_hclk_freq = __LL_RCC_CALC_HCLK_FREQ(CONFIG_CLOCK_STM32_HSE_CLOCK,
s_ClkInitStruct.AHBCLKDivider);
__ASSERT(new_hclk_freq == CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
"Config mismatch HCLK frequency %u %u",
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, new_hclk_freq);
/* If freq increases, set flash latency before any clock setting */
if (new_hclk_freq > old_hclk_freq) {
LL_SetFlashLatency(new_hclk_freq);
}
/* Enable HSE if not enabled */ /* Enable HSE if not enabled */
if (LL_RCC_HSE_IsReady() != 1) { if (LL_RCC_HSE_IsReady() != 1) {
/* Check if need to enable HSE bypass feature or not */ /* Check if need to enable HSE bypass feature or not */
@ -377,11 +372,6 @@ void config_src_sysclk_hse(LL_UTILS_ClkInitTypeDef s_ClkInitStruct)
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSE) { while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSE) {
} }
/* If freq not increased, set flash latency after all clock setting */
if (new_hclk_freq <= old_hclk_freq) {
LL_SetFlashLatency(new_hclk_freq);
}
#endif /* STM32_SYSCLK_SRC_HSE */ #endif /* STM32_SYSCLK_SRC_HSE */
} }
@ -392,26 +382,6 @@ void config_src_sysclk_msis(LL_UTILS_ClkInitTypeDef s_ClkInitStruct)
{ {
#ifdef STM32_SYSCLK_SRC_MSIS #ifdef STM32_SYSCLK_SRC_MSIS
uint32_t old_hclk_freq;
uint32_t new_hclk_freq;
old_hclk_freq = HAL_RCC_GetHCLKFreq();
/* Calculate new SystemCoreClock variable with MSI freq */
/* MSI freq is defined from RUN range selection */
new_hclk_freq = __LL_RCC_CALC_HCLK_FREQ(
get_msis_frequency(),
s_ClkInitStruct.AHBCLKDivider);
__ASSERT(new_hclk_freq == CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
"Config mismatch HCLK frequency %u %u",
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, new_hclk_freq);
/* If freq increases, set flash latency before any clock setting */
if (new_hclk_freq > old_hclk_freq) {
LL_SetFlashLatency(new_hclk_freq);
}
set_regu_voltage(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC); set_regu_voltage(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
/* Set MSIS as SYSCLCK source */ /* Set MSIS as SYSCLCK source */
@ -420,11 +390,6 @@ void config_src_sysclk_msis(LL_UTILS_ClkInitTypeDef s_ClkInitStruct)
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_MSIS) { while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_MSIS) {
} }
/* If freq not increased, set flash latency after all clock setting */
if (new_hclk_freq <= old_hclk_freq) {
LL_SetFlashLatency(new_hclk_freq);
}
#endif /* STM32_SYSCLK_SRC_MSIS */ #endif /* STM32_SYSCLK_SRC_MSIS */
} }
@ -437,22 +402,28 @@ void config_src_sysclk_hsi(LL_UTILS_ClkInitTypeDef s_ClkInitStruct)
clock_switch_to_hsi(s_ClkInitStruct.AHBCLKDivider); clock_switch_to_hsi(s_ClkInitStruct.AHBCLKDivider);
/* Set flash latency */
/* HSI used as SYSCLK, set latency to 0 */
LL_FLASH_SetLatency(LL_FLASH_LATENCY_0);
#endif /* STM32_SYSCLK_SRC_HSI */ #endif /* STM32_SYSCLK_SRC_HSI */
} }
int stm32_clock_control_init(const struct device *dev) int stm32_clock_control_init(const struct device *dev)
{ {
LL_UTILS_ClkInitTypeDef s_ClkInitStruct; uint32_t old_hclk_freq = 0;
int r = 0;
ARG_UNUSED(dev); ARG_UNUSED(dev);
/* configure clock for AHB/APB buses */ /* configure clock for AHB/APB buses */
config_bus_clk_init((LL_UTILS_ClkInitTypeDef *)&s_ClkInitStruct); config_bus_clk_init((LL_UTILS_ClkInitTypeDef *)&s_ClkInitStruct);
/* Current hclk value */
old_hclk_freq = __LL_RCC_CALC_HCLK_FREQ(get_startup_frequency(), LL_RCC_GetAHBPrescaler());
/* Set flash latency */
/* If freq increases, set flash latency before any clock setting */
if (old_hclk_freq < CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) {
LL_SetFlashLatency(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
}
/* Some clocks would be activated by default */ /* Some clocks would be activated by default */
config_enable_default_clocks(); config_enable_default_clocks();
@ -478,6 +449,12 @@ int stm32_clock_control_init(const struct device *dev)
return -ENOTSUP; return -ENOTSUP;
} }
/* Set FLASH latency */
/* If freq not increased, set flash latency after all clock setting */
if (old_hclk_freq >= CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) {
LL_SetFlashLatency(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
}
/* Update CMSIS variable */ /* Update CMSIS variable */
SystemCoreClock = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC; SystemCoreClock = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;